Ds4830a user’s guide – Maxim Integrated DS4830A Optical Microcontroller User Manual
Page 168
DS4830A User’s Guide
168
21.1.1.1 – Breakpoint 0 Register (BP0)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
BP0[15:0]
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s = special
The Breakpoint 0 register is accessible only via background mode read/write commands. Breakpoint registers BP0,
BP1, BP2, and BP3 serve as program memory address breakpoints. When DME bit is set in background mode, the
debug engine monitors the program-address bus activity while the CPU is executing the user program. If an address
match is detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
21.1.1.2 – Breakpoint 1 Register (BP1)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
BP1[15:0]
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s = special
The Breakpoint 1 register is accessible only via background mode read/write commands. Breakpoint registers BP0,
BP1, BP2, and BP3 serve as program memory address breakpoints. When DME bit is set in background mode, the
debug engine monitors the program-address bus activity while the CPU is executing the user program. If an address
match is detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
21.1.1.3 – Breakpoint 2 Register (BP2)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
BP2[15:0]
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s = special
The Breakpoint 2 register is accessible only via background mode read/write commands. Breakpoint registers BP0,
BP1, BP2, and BP3 serve as program memory address breakpoints. When DME bit is set in background mode, the
debug engine monitors the program-address bus activity while the CPU is executing the user program. If an address
match is detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
21.1.1.4 – Breakpoint 3 Register (BP3)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
BP3[15:0]
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s = special
The Breakpoint 3 register is accessible only via background mode read/write commands. Breakpoint registers BP0,
BP1, BP2, and BP3 serve as program memory address breakpoints. When DME bit is set in background mode, the
debug engine monitors the program-address bus activity while the CPU is executing the user program. If an address
match is detected, a break occurs, allowing the debug engine to take control of the CPU and enter debug mode.
21.1.1.5 – Breakpoint 4 Register (BP4)
The Breakpoint 4 register is accessible only via background mode read/write commands.
When REGE = 0: This register serves as one of the two data memory address breakpoints. When DME is set in
background mode, the debug engine will monitor the data memory address bus activity while the CPU is executing
the user program. If an address match is detected, a break occurs, allowing the debug engine to take over control of
the CPU and enter debug mode.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
BP4[15:0]
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Access
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s = special
When REGE = 1: This register serves as one of the two register breakpoints. A break occurs when the destination
register address for the executed instruction matches with the specified module and index. The destination module
is indicated by the M[3:0] bits and the register within that module is defined by the r[4:0] bits.