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3 – in-circuit debug peripheral registers, Ds4830a user’s guide – Maxim Integrated DS4830A Optical Microcontroller User Manual

Page 175

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DS4830A User’s Guide

175

21.3 – In-Circuit Debug Peripheral Registers

The following peripheral registers are used to control the in-circuit debug mode of the DS4830A. Addresses of
registers are given as “Mx[yy],” where x is the module number (from 0 to 5 decimal) and yy is the register index (from
00h to 1Fh hexadecimal). Fields in the bit definition tables are defined as follows:

● Name: Symbolic names of bits or bit fields in this register.

● Reset: The value of each bit in this register following a standard reset. If this field reads “unchanged,” the

given bit is unaffected by standard reset. If this field reads “s,” the given bit does not have a fixed 0 or 1 reset
value because its value is determined by another internal state or external condition.

● POR: If present this field defines the value of each bit in this register following a power-on reset (as opposed

to a standard reset). Some bits are unaffected by standard resets and are set/cleared by POR only.

● Access: Bits can be read-only (r) or read/write (rw). Any special restrictions or conditions that could apply

when reading or writing this bit are detailed in the bit description.


21.3.1 – In-Circuit Debug Temp 0 Register (ICDT0, M2[18h])

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

ICDT0[15:0]

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Access

s

s

s

s

s

s

s

s

s

s

s

s

s

s

s

s

s = special


This register is read/write accessible by the CPU only in background mode or debug mode. This register is intended
for use by the utility ROM routines as temporary storage to save registers that might otherwise have to be placed in
the stack.

21.3.2 – In-Circuit Debug Temp 1 Register (ICDT1, M2[19h])

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

ICDT1[15:0]

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Access

s

s

s

s

s

s

s

s

s

s

s

s

s

s

s

s

s = special


This register is read/write accessible by the CPU only in background mode or debug mode. This register is intended
for use by the utility ROM routines as temporary storage to save registers that might otherwise have to be placed in
the stack.