Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 169)

DS4830A User’s Guide
169
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name - - - - - - - r.4 r.3 r.2 r.1 r.0 M.3 M.2 M.1 M.0
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Access s s s s s s s s s s s s s s s s
s = special
21.1.1.6 – Breakpoint 5 Register (BP5)
The Breakpoint 5 register is accessible only via background mode read/write commands.
When REGE = 0: This register serves as one of the two data memory address breakpoints. When DME is set in
background mode, the debug engine will monitor the data memory address bus activity while the CPU is executing
the user program. If an address match is detected, a break occurs, allowing the debug engine to take over control of
the CPU and enter debug mode.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name BP5[15:0]
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Access s s s s s s s s* s* s* s* s* s** s** s** s**
s = special
When REGE = 1: This register serves as one of the two register breakpoints. The destination module is indicated by
the M[3:0] bits and the register within that module is defined by the r[4:0] bits. A break occurs when two following
conditions are met:
• The destination register address for the executed instruction matches with the specified module and index.
• The bit pattern written to the destination register matches those bits specified for comparison by the ICDD
data register and ICDA mask register. Only those ICDD data bits with their corresponding ICDA mask bits
will be compared. When all bits in the ICDA register are cleared, Condition 2 becomes a don’t care.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name - - - - - - - r.4 r.3 r.2 r.1 r.0 M.3 M.2 M.1 M.0
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Access s s s s s s s s s s s s s s s s
s = special
21.1.2 – Using Breakpoints
All breakpoint registers (BP0-BP5) default to the FFFFh state on power-on reset or when the Test-Logic-Reset TAP
state is entered. The breakpoint registers are accessible only with Background mode read/write commands issued
over the TAP communication link. The breakpoint registers are not read/write accessible to the CPU.
Setting the Debug Mode Enable (DME) bit in the ICDC register to logic 1 enables all six breakpoint registers for
breakpoint match comparison. The state of the Break-On Register Enable (REGE) bit in the ICDC register
determines whether the BP4 and BP5 breakpoints should be used as data memory address breakpoints (REGE = 0)
or as register breakpoints (REGE = 1).
When using the register matching breakpoints, it is important to realize that Debug mode operations (e.g., read data
memory, write data memory, etc.) require use of ICDA and ICDD for passing of information between the host and
DS4830A ROM routines. It is advised that these registers be saved and restored or be reconfigured before returning
to the background mode if register breakpoints are to remain enabled.
When a breakpoint match occurs, the debug engine forces a break and the DS4830A enters Debug Mode. If a
breakpoint match occurs on an instruction that activates the PFX register, the break is held off until the prefixed
operation completes. The host can assess whether Debug mode has been entered by monitoring the status bits of
the 10-bit word shifted out of the TDO pin. The status bits will change from the Non-debug (00b) state associated
with background mode to the Debug-Idle (01b) state when Debug Mode is entered. Debug mode can also be
manually invoked by host issuance of the 'Debug' background command.