Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 24)

DS4830A User’s Guide
24
2.6.4 – Internal System Resets
There are two possible sources of internal system resets. An internal reset will hold the DS4830A in reset mode for 12
clock cycles.
1. When data BBh is written to the special I
2
C slave address 34h.
2. When in-system programming is complete and the ROD bit is set to 1.
2.6.5 – Software Reset
The device UROM provides option to soft reset through the application program. The application program jumps to UROM
code which generates the internal system reset. UROM location 8854h has code when executed generates internal reset.
Application program can jump to this location to generate software reset.
asm (“LJUMP #8854h”)
2.7 – Clock Generation
The DS4830A generates its 20MHz peripheral clock using an internal oscillator and generates 10MHz instruction clock
using divide by 2 circuit. This oscillator starts up when V
DD
exceeds the brownout voltage level, V
BO
. There is a delay of
approximately 1ms in the oscillator start up and beginning of clock. This delay ensures that the clock is stable prior to
beginning normal operation.