Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 113)

DS4830A User’s Guide
113
12.1.2 – SPI Character Lengths
To flexibly accommodate different SPI transfer data lengths, the character length for any transfer is user configurable
via the Character Length Bit (CHR) in the SPI Configuration Register. These are independently configurable for the
master and slave SPI. The CHR bit allows selection of either 8-bit or 16-bit transfers. When CHR is 0, the character
length is 8-bits; when CHR is set to 1, the character length is 16 bits.
When loading 8-bit characters into the SPIB data buffer, the byte for transmission should be right-justified or placed
in the least significant byte of the word. When a byte transfer completes, the received byte is right-justified and can
be read from the least significant byte of the SPIB word. The most significant byte of the SPIB data buffer is not used
when transmitting and receiving 8-bit characters.
12.2 – SPI System Errors
Three types of SPI system errors can be detected by the SPI module. A mode fault error arises in a multiple master
system when more than one SPI device simultaneously tries to be a master. A receive overrun error occurs when an
SPI transfer completes before the previous character has been read from the receive data buffer. The third kind of
error, write collision, indicates that an attempted write to SPIB was detected while a transfer was in progress
(STBY=1).
12.2.1 – Mode Fault
When a SPI device is configured as a master and its Mode Fault Enable bit (SPICN.2: MODFE) is also set, the Slave
Select pin is configured as input for mode fault detection. The mode fault error occurs if Slave Select signal is
asserted by an external device. This error can occur in multi master system when a second SPI device attempts to
function as a master in the system. This causes the possibility of contention, which may damage the CMOS push
pull drivers. The active state of Slave Select is defined by Slave Active Select bit (SPICF.6: SAS). If SAS is cleared
to 0 and a low SSEL input signal is detected while MODFE is set, a mode fault error has occurred. If SAS is set to 1,
a high SSEL signal indicates that a mode fault error has occurred. The mode fault error detection is to provide
protection from such damage by disabling the bus drivers. When a mode fault is detected, the following actions are
taken immediately by hardware:
1. The MSTM bit is forced to 0 to reconfigure the SPI device as a slave.
2. The SPIEN bit is forced to 0 to disable the SPI module.
3. The Mode Fault (SPICN.3: MODF) status flag is set. Setting the MODF bit can generate an interrupt if it is
enabled.
The application software must correct the system conflict before resuming its normal operation. The MODF flag is set
automatically by hardware but must be cleared by software or a reset once set. Setting the MODF bit to 1 by
software causes an interrupt if enabled.
Mode fault detection is optional and can be disabled by clearing the MODFE bit to 0. Disabling the mode fault
detection will disable the function of the Slave Select signal during the master mode operation, allowing the
associated port pin to be used as a general-purpose I/O.
Note that the mode fault mechanism does not provide full protection from bus contention in multiple master, multiple
slave systems. For example, if two devices are configured as master at the same time, the mode fault-detect circuitry
offers protection only when one of them selects the other as slave by asserting its Slave Select signal. Also, if a
master accidentally activates more than one slave and those devices try to simultaneously drive their output pins,
bus contention can occur without a mode fault error being generated.
12.2.2 – Receive Overrun
Since the receive direction of SPI is double buffered, there is no overrun condition as long as the received character
in the read buffer is read before the next character in the shift register is ready to be transferred to the read buffer.
However, if previous data in the read buffer has not been read out when a transfer cycle is completed and the new
character is loaded into the read buffer, a receive overrun occurs and the Receive Overrun flag (SPICN.5: ROVR)
will be set. Setting the ROVR flag indicates that the newer received character has been overwritten and is lost.
Setting the ROVR bit to 1 will cause an interrupt if enabled. Once set, the ROVR bit is cleared only by software or a
reset.