Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 28)

DS4830A User’s Guide
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3.4 – Interrupt and Control Register (IC, 08h[05h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
Bit Name Function
7:2 Reserved Reserved. All reads return 0.
1 INS
Interrupt In Service. The INS is set by hardware automatically when an interrupt is acknowledged. No
further interrupts occur as long as the INS remains set. The interrupt service routine can clear the INS
bit to allow interrupt nesting. Otherwise, the INS bit is cleared by hardware upon execution of an RETI
or POPI instruction.
0 IGE
Interrupt Global Enable. If this bit is set to 1, interrupts are globally enabled, but still must be locally
enabled to occur. If this bit is set to 0, all interrupts are disabled.
3.5 – Interrupt Mask Register (IMR, 08h[06h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted read/write access.
Bit Name Function
7 IMS Interrupt Mask for System Modules
6 Reserved Reserved. All reads return 0.
5 IM5 Interrupt Mask for Register Module 5
4 IM4 Interrupt Mask for Register Module 4
3 IM3 Interrupt Mask for Register Module 3
2 IM2 Interrupt Mask for Register Module 2
1 IM1 Interrupt Mask for Register Module 1
0 IM0 Interrupt Mask for Register Module 0
The first six bits in this register are interrupt mask bits for modules 0 to 5, one bit per module. The eighth bit, IMS, serves
as a mask for any system module interrupt sources. Setting a mask bit allows the enabled interrupt sources for the
associated module or system (for the case of IMS) to generate interrupt requests. Clearing the mask bit effectively
disables all interrupt sources associated with that specific module or all system interrupt sources (for the case of IMS).
The interrupt mask register is intended to facilitate user-definable interrupt prioritization.
3.6 – System Control Register (SC, 08h[08h])
Initialization: This register is reset to 1000 00s0b on all reset. Bit 1 (PWL) is set to 1 on a power-on reset only.
Access: Unrestricted read/write access.
Bit Name Function
7 TAP
Test Access Port (JTAG) Enable. This bit controls whether the Test Access Port special-function pins
are enabled. The TAP defaults to being enabled. Clearing this bit to 0 disables the TAP special
function pins.
6:5 Reserved Reserved. All reads return 0.
4 CDA0
Code Data Access Bit 0.
The CDA0 bit is used to logically map the flash memory pages to the data space for read/write access.
The logical data memory addresses of the flash depend on whether execution is from Utility ROM or
SRAM. The CDA0 bit is not needed if data memory is accessed in word mode.
CDA0 Byte Mode Active Page Word Mode Active Page
0 P0 P0 and P1
1 P1 P0 and P1
3 Reserved Reserved. All reads return 0.
2 ROD
ROM Operation Done. This bit is used to signify completion of a ROM operation sequence to the
control units. This allows the Debug engine to determine the status of a ROM sequence. Setting this
bit to logic 1 causes an internal system reset if the JTAG SPE bit is also set. Setting the ROD bit will
clear the JTAG SPE and I2C_SPE bits if set. The ROD bit will be automatically cleared by hardware
once the control unit acknowledges the done indication.
1 PWL
Password Lock. This bit defaults to 1 on a power-on reset. When this bit is 1, it requires a 32-byte
password to be matched with the password in the program space before allowing access to the
password protected in-circuit debug or bootstrap loader ROM routines. Clearing this bit to 0 disables
the password protection for these ROM routines.
0 Reserved Reserved. All reads return 0.