Samsung S3F401F User Manual
Page 54
ENCODER COUNTER
S3F401F_UM_REV1.00
4-6
Encoder Counter Control Register 0 (Continued) ENCCON0 (0x000)
Access: Read/Write
PZCLEN
PCNT Clear Enable by Phase Z.
0 = Enable
1 = Disable
ENCCLKSEL
Encoder Counter Clock (DECCLK) Selection Field
000 = ENCCLK
100 = ENCCLK /16
001 = ENCCLK /2
101 = ENCCLK /32
010 = ENCCLK /4
110 = ENCCLK /64
011 = ENCCLK /8
111 = ENCCLK /128
DBGEN
Debug Enable Bit
0 = ENC is halted during processor debug mode.
1 = ENC is not halted during processor debug mode. Although you break the debugger, you
can see count register and several bits of status register changing according to the operation
setting.
NOTE
Several bits of status - These bits are ENCSTATUS.0, ENCSTATUS.2 and ENCSTATUS.3. Because
these bits can a read-only bit.
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