Samsung S3F401F - Manual (Page 250)

UART S3F401F_UM_REV1.00
12-12
3.8.1 UARTRXINTR
The receive interrupt changes state when one of the following events occurs:
• IFO
MODE
UARTRXINTR interrupt is asserted HIGH. Å The receive FIFO reaches the programmed trigger level.
UARTRXINTR interrupt is cleared. Å By reading data from the receive FIFO until less than the trigger level
Or by clearing the interrupt
• ON-FIFO MODE
UARTRXINTR interrupt is asserted HIGH. Å The data is received thereby filling the location.
UARTRXINTR interrupt is cleared. Å By performing a single read of the receive FIFO,
Or by clearing the interrupt
3.8.2 UARTTXINTR
The transmit interrupt changes state when one of the following events occurs:
• If the FIFOs are enabled and the transmit FIFO reaches the programmed trigger level. When this happens,
the transmit interrupt is asserted HIGH. The transmit interrupt is cleared by writing data to the transmit FIFO
until it becomes greater than the trigger level, or by clearing the interrupt.
• If the FIFOs are disabled (have a depth of one location) and there is no data present in the transmitters single
location, the transmit interrupt is asserted HIGH. It is cleared by performing a single write to the transmit
FIFO, or by clearing the interrupt.
To update the transmit FIFO you must:
• Write data to the transmit FIFO, either prior to enabling the UART and the interrupts, or after enabling the
UART and interrupts.
NOTE: The transmit interrupt is based on a transition through a level, rather than on the level itself. When the
interrupt and the UART is enabled before any data is written to the transmit FIFO the interrupt is not set. The interrupt
is only set once written data leaves the single location of the transmit FIFO and it becomes empty.