Samsung S3C8275X User Manual

Samsung Hardware

S3C8275X/F8275X/C8278X

/F8278X/C8274X/F8274X

8-BIT CMOS

MICROCONTROLLERS

USER'S MANUAL

Revision 1.4

This manual is related to the following products:

F8278X F8275X C8278X C8274X F8274X

Table of contents

Document Outline

NOTIFICATION OF REVISIONS
Table of Contents
List of Figures
List of Tables
List of Programming Tips
List of Register Descriptions
List of Instruction Descriptions
1 PRODUCT OVERVIEW
- S3C8-SERIES MICROCONTROLLERS
- S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X MICROCONTROLLER
- FLASH
- FEATURES
- BLOCK DIAGRAM
- PIN ASSIGNMENT
- PIN DESCRIPTIONS
- PIN CIRCUITS
- Figure 1-1. Block Diagram
- Figure 1-2. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments (64-QFP-1420F)
- Figure 1-3. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Assignments (64-LQFP-1010)
- Figure 1-4. Pin Circuit Type A
- Figure 1-5. Pin Circuit Type B (nRESET)
- Figure 1-6. Pin Circuit Type E-4 (P0, P1)
- Figure 1-7. Pin Circuit Type H-4
- Figure 1-8. Pin Circuit Type H-8 (P2.1– P2.7, P3)
- Figure 1-9. Pin Circuit Type H-9 (P4, P5, P6)
- Figure 1-10. Pin Circuit Type H-10 (P2.0)
- Table 1-1. S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X Pin Descriptions
2 ADDRESS SPACES
- OVERVIEW
- PROGRAM MEMORY (ROM)
  - SMART OPTION
- REGISTER ARCHITECTURE
  - REGISTER PAGE POINTER (PP)
    - PROGRAMMING TIP — Using the Page Pointer for RAM Clear (Page 0, Page 1)
  - REGISTER SET 1
  - REGISTER SET 2
  - PRIME REGISTER SPACE
  - WORKING REGISTERS
  - USING THE REGISTER POINTS
    - PROGRAMMING TIP — Setting the Register Pointers
    - PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers
- REGISTER ADDRESSING
  - COMMON WORKING REGISTER AREA (C0H–CFH)
    - PROGRAMMING TIP — Addressing the Common Working Register Area
  - 4-BIT WORKING REGISTER ADDRESSING
  - 8-BIT WORKING REGISTER ADDRESSING
- SYSTEM AND USER STACK
  - Programming TIP — Standard Stack Operations Using PUSH and POP
- Figure 2-1. Program Memory Address Space
- Figure 2-2. Smart Option
- Figure 2-3. Internal Register File Organization (S3C8275X)
- Figure 2-4. Internal Register File Organization (S3C8278X/C8274X)
- Figure 2-5. Register Page Pointer (PP)
- Figure 2-6. Set 1, Set 2, Prime Area Register, and LCD Data Register Map
- Figure 2-7. 8-Byte Working Register Areas (Slices)
- Figure 2-8. Contiguous 16-Byte Working Register Block
- Figure 2-9. Non-Contiguous 16-Byte Working Register Block
- Figure 2-10. 16-Bit Register Pair
- Figure 2-11. Register File Addressing
- Figure 2-12. Common Working Register Area
- Figure 2-13. 4-Bit Working Register Addressing
- Figure 2-14. 4-Bit Working Register Addressing Example
- Figure 2-15. 8-Bit Working Register Addressing
- Figure 2-16. 8-Bit Working Register Addressing Example
- Figure 2-17. Stack Operations
- Table 2-1. S3C8275X Register Type Summary
- Table 2-2. S3C8278X/C8274X Register Type Summary
3 ADDRESSING MODES
- OVERVIEW
- REGISTER ADDRESSING MODE (R)
- INDIRECT REGISTER ADDRESSING MODE (IR)
- INDEXED ADDRESSING MODE (X)
- DIRECT ADDRESS MODE (DA)
- INDIRECT ADDRESS MODE (IA)
- RELATIVE ADDRESS MODE (RA)
- IMMEDIATE MODE (IM)
- Figure 3-1. Register Addressing
- Figure 3-2. Working Register Addressing
- Figure 3-3. Indirect Register Addressing to Register File
- Figure 3-4. Indirect Register Addressing to Program Memory
- Figure 3-5. Indirect Working Register Addressing to Register File
- Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
- Figure 3-7. Indexed Addressing to Register File
- Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
- Figure 3-9. Indexed Addressing to Program or Data Memory
- Figure 3-10. Direct Addressing for Load Instructions
- Figure 3-11. Direct Addressing for Call and Jump Instructions
- Figure 3-12. Indirect Addressing
- Figure 3-13. Relative Addressing
- Figure 3-14. Immediate Addressing
4 CONTROL REGISTERS
- BLDCON — Battery Level Detector Control Register
- BTCON — Basic Timer Control Register
- CLKCON — System Clock Control Register
- CLOCON — Clock Output Control Register
- EXTICONH — External Interrupt Control Register (High Byte)
- EXTICONL — External Interrupt Control Register (Low Byte)
- EXTIPND — External Interrupt Pending Register
- FLAGS — System Flags Register
- FMCON — Flash Memory Control Register
- FMSECH — Flash Memory Sector Address Register (High Byte)
- FMSECL — Flash Memory Sector Address Register (Low Byte)
- FMUSR — Flash Memory User Programming Enable Register
- IMR — Interrupt Mask Register
- IPH — Instruction Pointer (High Byte)
- IPL — Instruction Pointer (Low Byte)
- IPR — Interrupt Priority Register
- IRQ — Interrupt Request Register
- LCON — LCD Control Register
- OSCCON — Oscillator Control Register
- P0CONH — Port 0 Control Register (High Byte)
- P0CONL — Port 0 Control Register (Low Byte)
- P0PUR — Port 0 Pull-Up Control Register
- P1CONH — Port 1 Control Register (High Byte)
- P1CONL — Port 1 Control Register (Low Byte)
- P1PUR — Port 1 Pull-up Control Register
- P2CONH — Port 2 Control Register (High Byte)
- P2CONL — Port 2 Control Register (Low Byte)
- P2PUR — Port 2 Pull-up Control Register
- P3CONH — Port 3 Control Register (High Byte)
- P3CONL — Port 3 Control Register (Low Byte)
- P3PUR — Port 3 Pull-up Control Register
- P4CONH — Port 4 Control Register (High Byte)
- P4CONL — Port 4 Control Register (Low Byte)
- P5CONH — Port 5 Control Register (High Byte)
- P5CONL — Port 5 Control Register (Low Byte)
- P6CON — Port 6 Control Register
- PP — Register Page Pointer
- RP0 — Register Pointer 0
- RP1 — Register Pointer 1
- SIOCON — SIO Control Register
- SPH — Stack Pointer (High Byte)
- SPL — Stack Pointer (Low Byte)
- STPCON — Stop Control Register
- SYM — System Mode Register
- TACON — Timer 1/A Control Register
- TBCON — Timer B Control Register
- WTCON — Watch Timer Control Register
- Figure 4-1. Register Description Format
- Table 4-1. Set 1 Registers
- Table 4-2. Set 1, Bank 0 Registers
- Table 4-3. Set 1, Bank 1 Registers
5 INTERRUPT STRUCTURE
- OVERVIEW
- Figure 5-1. S3C8-Series Interrupt Types
- Figure 5-2. S3C8275X/C8278X/C8274X Interrupt Structure
- Figure 5-3. ROM Vector Address Area
- Figure 5-4. Interrupt Function Diagram
- Figure 5-5. System Mode Register (SYM)
- Figure 5-6. Interrupt Mask Register (IMR)
- Figure 5-7. Interrupt Request Priority Groups
- Figure 5-8. Interrupt Priority Register (IPR)
- Figure 5-9. Interrupt Request Register (IRQ)
- Table 5-1. Interrupt Vectors
- Table 5-2. Interrupt Control Register Overview
- Table 5-3. Interrupt Source Control and Data Registers
6 INSTRUCTION SET
- OVERVIEW
- Figure 6-1. System Flags Register (FLAGS)
- Table 6-1. Instruction Group Summary
- Table 6-2. Flag Notation Conventions
- Table 6-3. Instruction Set Symbols
- Table 6-4. Instruction Notation Conventions
- Table 6-5. Opcode Quick Reference
- Table 6-6. Condition Codes
7 CLOCK CIRCUIT
- OVERVIEW
- Figure 7-1. Crystal/Ceramic Oscillator (fx)
- Figure 7-2. External Oscillator (fx)
- Figure 7-3. RC Oscillator (fx)
- Figure 7-4. Crystal Oscillator (fxt)
- Figure 7-5. External Oscillator (fxt)
- Figure 7-6. System Clock Circuit Diagram
- Figure 7-7. System Clock Control Register (CLKCON)
- Figure 7-8. Clock Output Control Register (CLOCON)
- Figure 7-9. Clock Output Block Diagram
- Figure 7-10. Oscillator Control Register (OSCCON)
- Figure 7-11. STOP Control Register (STPCON)
8 RESET and POWER-DOWN
- SYSTEM RESET
- POWER-DOWN MODES
  - STOP MODE
  - IDLE MODE
- Table 8-1. S3C8275X/C8278X/C8274X Set 1 Register and Values After RESET
- Table 8-2. S3C8275X/C8278X/C8274X Set 1, Bank 0 Register Values After RESET
- Table 8-3. S3C8275X/C8278X/C8274X Set 1, Bank 1 Register Values After RESET
9 I/O PORTS
- OVERVIEW
  - PORT DATA REGISTERS
  - PORT 0
  - PORT 1
  - PORT 2
  - PORT 3
  - PORT 4
  - PORT 5
  - PORT 6
- Figure 9-1. S3C8275X/C8278X/C8274X I/O Port Data Register Format
- Figure 9-2. Port 0 High-Byte Control Register (P0CONH)
- Figure 9-3. Port 0 Low-Byte Control Register (P0CONL)
- Figure 9-4. Port 0 Pull-up Control Register (P0PUR)
- Figure 9-5. External Interrupt Control Register, Low Byte (EXTICONL)
- Figure 9-6. External Interrupt Pending Register (EXTIPND)
- Figure 9-7. Port 1 High-Byte Control Register (P1CONH)
- Figure 9-8. Port 1 Low-Byte Control Register (P1CONL)
- Figure 9-9. Port 1 Pull-up Control Register (P1PUR)
- Figure 9-10. External Interrupt Control Register, High Byte (EXTICONH)
- Figure 9-11. External Interrupt Control Register, Low Byte (EXTICONL)
- Figure 9-12. External Interrupt Pending Register (EXTIPND)
- Figure 9-13. Port 2 High-byte Control Register (P2CONH)
- Figure 9-14. Port 2 Low-byte Control Register (P2CONL)
- Figure 9-15. Port 2 Pull-up Control Register (P2PUR)
- Figure 9-16. Port 3 High Byte Control Register (P3CONH)
- Figure 9-17. Port 3 Low Byte Control Register (P3CONL)
- Figure 9-18. Port 3 Pull-up Control Register (P3PUR)
- Figure 9-19. Port 4 High-Byte Control Register (P4CONH)
- Figure 9-20. Port 4 Low-Byte Control Register (P4CONL)
- Figure 9-21. Port 5 High-Byte Control Register (P5CONH)
- Figure 9-22. Port 5 Low-Byte Control Register (P5CONL)
- Figure 9-23. Port 6 Control Register (P6CON)
- Table 9-1. S3C8275X/C8278X/C8274X Port Configuration Overview
- Table 9-2. Port Data Register Summary
10 BASIC TIMER
- OVERVIEW
  - BASIC TIMER CONTROL REGISTER (BTCON)
  - BASIC TIMER FUNCTION DESCRIPTION
- Figure 10-1. Basic Timer Control Register (BTCON)
- Figure 10-2. Basic Timer Block Diagram
11 TIMER 1
- ONE 16-BIT TIMER MODE (TIMER 1)
  - OVERVIEW
  - FUNCTION DESCRIPTION
- TWO 8-BIT TIMERS MODE (TIMER A and B)
  - OVERVIEW
  - FUNCTION DESCRIPTION
- Figure 11-1. Timer 1/A Control Register (TACON)
- Figure 11-2. Timer 1 Block Diagram (One 16-bit Mode)
- Figure 11-3. Timer 1/A Control Register (TACON)
- Figure 11-4. Timer B Control Register (TBCON)
- Figure 11-5. Timer A Block Diagram (Two 8-bit Timers Mode)
- Figure 11-6. Timer B Block Diagram (Two 8-bit Timers Mode)
12 WATCH TIMER
- OVERVIEW
  - WATCH TIMER CONTROL REGISTER (WTCON)
  - WATCH TIMER CIRCUIT DIASGRAM
- Figure 12-1. Watch Timer Control Register (WTCON)
- Figure 12-2. Watch Timer Circuit Diagram
13 LCD CONTROLLER/DRIVER
- OVERVIEW
- Figure 13-1. LCD Function Diagram
- Figure 13-2. LCD Circuit Diagram
- Figure 13-3. LCD Display Data RAM Organization
- Figure 13-4. LCD Control Register (LCON)
- Figure 13-5. Internal Voltage Dividing Resistor Connection
- Figure 13-6. Select/No-Select Signals in Static Display Mode
- Figure 13-7. Select/No-Select Signal in 1/2 Duty, 1/2 Bias Display Mode
- Figure 13-8. Select/No-Select Signal in 1/3 Duty, 1/3 Bias Display Mode
- Figure 13-9. LCD Signals and Wave Forms Example in 1/4 Duty, 1/3 Bias Display Mode
14 SERIAL I/O INTERFACE
- OVERVIEW
- SIO BLOCK DIAGRAM
  - SERIAL I/O TIMING DIAGRAM (SIO)
- Figure 14-1. Serial I/O Module Control Register (SIOCON)
- Figure 14-2. SIO Prescaler Register (SIOPS)
- Figure 14-3. SIO Functional Block Diagram
- Figure 14-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)
- Figure 14-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)
15 BATTERY LEVEL DETECTOR
- OVERVIEW
  - BATTERY LEVEL DETECTOR CONTROL REGISTER (BLDCON)
- Figure 15-1. Block Diagram for Voltage Level Detect
- Figure 15-2. Battery Level Detect Circuit and Control Register
- Table 15-1. BLDCON Value and Detection Level
16 EMBEDDED FLASH MEMORY INTERFACE
- OVERVIEW
- USER PROGRAM MODE
  - FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE)
- ISPTM (ON-BOARD PROGRAMMING) SECTOR
- SECTOR ERASE
  - PROGRAMMING TIP ⎯ Sector Erase
- PROGRAMMING
  - PROGRAMMING TIP ⎯ Program
- READING
  - PROGRAMMING TIP ⎯ Reading
- HARD LOCK PROTECTION
  - PROGRAMMING TIP ⎯ Hard Lock Protection
- Figure 16-1. Flash Memory Control Register (FMCON)
- Figure 16-2. Flash Memory User Programming Enable Register (FMUSR)
- Figure 16-3. Flash Memory Sector Address Register, High Byte (FMSECH)
- Figure 16-4. Flash Memory Sector Address Register, Low Byte (FMSECL)
- Figure 16-5. Program Memory Address Space
- Figure 16-6. Sector Configurations in User Program Mode
- Table 16-1. ISP Sector Size
- Table 16-2. Reset Vector Address
17 ELECTRICAL DATA
- Figure 17-1. Stop Mode Release Timing When Initiated by an External Interrupt
- Figure 17-2. Stop Mode Release Timing When Initiated by a RESET
- Figure 17-3. Input Timing for External Interrupts
- Figure 17-4. Input Timing for RESET
- Figure 17-5. Serial Data Transfer Timing
- Figure 17-6. LVR (Low Voltage Reset) Timing
- Figure 17-7. Clock Timing Measurement at XIN
- Figure 17-8. Clock Timing Measurement at XTIN
- Figure 17-9. Operating Voltage Range
- Table 17-1. Absolute Maximum Ratings
- Table 17-2. D.C. Electrical Characteristics
- Table 17-3. Data Retention Supply Voltage in Stop Mode
- Table 17-4. Input/Output Capacitance
- Table 17-5. A.C. Electrical Characteristics
- Table 17-6. Battery Level Detector Electrical Characteristics
- Table 17-7. LVR (Low Voltage Reset) Electrical Characteristics
- Table 17-8. Main Oscillation Characteristics
- Table 17-9. Sub Oscillation Characteristics
- Table 17-10. Main Oscillation Stabilization Time
- Table 17-11. Sub Oscillation Stabilization Time
- Table 17-12. A.C. Electrical Characteristics for Internal Flash ROM
18 MECHANICAL DATA
- Figure 18-1. 64-Pin QFP Package Dimensions (64-QFP-1420F)
- Figure 18-2. 64-Pin LQFP Package Dimensions (64-LQFP-1010)
19 S3F8275X/F8278X/F8274X FLASH MCU
- OVERVIEW
  - OPERATING MODE CHARACTERISTICS
- Figure 19-1. S3F8275X/F8278X/F8274X Pin Assignments (64-QFP-1420F)
- Figure 19-2. S3F8275X/F8278X/F8274X Pin Assignments (64-LQFP-1010)
- Figure 19-3. Operating Voltage Range
- Table 19-1. Descriptions of Pins Used to Read/Write the Flash ROM
- Table 19-2. Comparison of S3F8275X/F8278X/F8274X and S3C8275X/C8278X/C8274X Features
- Table 19-3. Operating Mode Selection Criteria
- Table 19-4. D.C. Electrical Characteristics
20 DEVELOPMENT TOOLS
- OVERVIEW
- Figure 20-1. SMDS Product Configuration (SMDS2+)
- Figure 20-2. TB8275/8/4 Target Board Configuration
- Figure 20-3. 40-Pin Connectors (J101, J102) for TB8275/8/4
- Figure 20-4. S3E8270 Cables for 64-QFP Package
- Table 20-1. Power Selection Settings for TB8275/8/4
- Table 20-2. Main-clock Selection Settings for TB8275/8/4
- Table 20-3. Select Smart Option Source Setting for TB8275/8/4
- Table 20-4. Smart Option Switch Settings for TB8275/8/4
- Table 20-5. Device Selection Settings for TB8275/8/4
- Table 20-6. The SMDS2+ Tool Selection Setting