Samsung S3F401F - Manual (Page 251)

S3F401F_UM_REV1.00 UART
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3.8.3 UARTRTINTR
The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received over
a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all
the data (or by reading the holding register), or when a 1 is written to the corresponding bit of the UARTICR
register.
3.8.4 UARTEINTR
The error interrupt is asserted when an error occurs in the reception of data by the UART. The interrupt can be
caused by a number of different error conditions:
• framing
• parity
• break
• overrun.
You can determine the cause of the interrupt by reading the UARTRIS or UARTMIS registers. It can be cleared by
writing to the relevant bits of the UARTICR register (bits 7 to 10 are the error clear bits).