Samsung S3F401F User Manual
Page 234
TIMER
S3F401F_UM_REV1.00
11-10
Timer Control Register (Continued)
TCON (0x000)
Access: Read/Write
TEN
Timer Enable Bit
0 = Disable
Timer Stop
1 = Enable
Timer Start
T_CAPFTON
Filter Enable Bit on for TCAP Input Control Bit
0 = Disable
1 = Enable
T_CLKFTON
Filter Enable Bit on for TCLK Input Control Bit
0 = Disable
1 = Enable
NOTE
The all bits of TCON except TEN and CL can be changed only when TEN is set to 0. (Timer stop)
If TEN is 0 and CL is set to 1, counter is cleared when TEN is set to 1.
The size of filter for TCLK input is 10ns. The size of filter for TCAP input is min {3x1/PCLK, 2x1/TCLK}.
Before TEN is set to 1 after reset, the output level of configured PWM port is low regardless of IVT. When
TEN is set to 0 after TEN is set to 1, the level of PWM is sustained previous level.
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