Samsung S3F401F - Manual (Page 31)

A/D CONVERTER S3F401F_UM_REV1.00
2-4
3.1.2 A/D Conversion
3.1.2.1 The Sampling Mode
S3F401F
′s ADC can get the result of maximum 3 converted digital data at one time. In other means, user can get
the AD conversion data one, two or three by one conversion. This is determined the ADC Mode Selection Bits in
ADCCON register.
MODESEL[1:0] Description Active Channel
0 0
′b
3-point simultaneous sampling SHA1 SHA2 SHA3
0 1
′b
1-point sampling SHA1
− −
1 0
′b
2-point simultaneous sampling SHA1 SHA2
−
1 1
′b
Reserved
− − −
3.1.2.2 The Conversion Start
The ADC conversion can be started by 3 triggered sources. Start trigger source is determined by TRIGSEL[1:0]
bits in ADCCON register. User should select the corresponding value each application.
a. Software Command
b. Inverter Motor Control Block (IMC) trigger signal
c. External Signal inserted into ADCTRG pin.
3.1.2.3 The End of Conversion
After finishing the conversion, user can catch the valid data by reading each result register. The end of conversion
is informed by the value of EOC bit in the interrupt pending register. So after ADC conversion, user should check
EOC pending bit and clear.
3.1.2.4 The Conversion Time
When the external/internal clock (Fin) frequency is 8MHz and the divider value is ‘1’ (Fin/2), total 12-bit conversion
time is as follows:
A/D converter clock = 8MHz / 2 = 4MHz
Conversion speed = 4MHz / 11cycles = 363.6 kHz
→ Conversion time = 2.75 us
NOTES:
1. This A/D converter was designed to operate at maximum 4MHz clock. If 1xchannel is selected for ADC conversion
(ADCCON.9-.8 = 01), maximum 9xclocks are needed for ADC conversion. If 2xchannels are selected for ADC conversion
(ADCCON.9-.8 = 10), maximum 10xclocks are needed for ADC conversion. If 3xchannels are selected for ADC
conversion (ADCCON.9-.8 = 00), maximum 11xclocks are needed for ADC conversion.
2. ADCCLK source is Fin , not PCLK. ADCCLK must be less than PCLK or equal.