Samsung S3F401F - Manual (Page 206)

S3F401F_UM_REV1.00 SSP
10-5
2.1.3 Transmit and Receive Logic
To configure the SSP as a master, clear the SSPCR1 register master or slave selection bit (MS) to 0, which is the
default value on reset. Setting the SSPCR1 register MS bit to 1 configures the SSP as a slave. When configured as
a slave, enabling or disabling of the SSP SSPTXD signal is provided through the SSPCR1 slave mode SSPTXD
output disable bit (SOD). This can be used in some multi-slave environments where masters might parallel
broadcast.
To enable the operation of the SSP set the Synchronous Serial Port Enable (SSE) bit to 1.
When configured as a master, the clock to the attached slaves is derived from a divided down version of PCLK
through the prescaler operations described previously. The master transmit logic successively reads a value from its
transmit FIFO and performs parallel to serial conversion on it. Then the serial data stream and frame control signal,
synchronized to SSPCLK, are output through the SSPTXD to the attached slaves. The master receive logic
performs serial to parallel conversion on the incoming synchronous SSPRXD data stream, extracting and storing
values into its receive FIFO, for subsequent reading through the APB interface.
When configured as a slave, the SSPCLK clock is provided by an attached master and used to time its transmission
and reception sequences. The slave transmit logic, under control of the master clock, successively reads a value
from its transmit FIFO, performs parallel to serial conversion, then output the serial data stream and frame control
signal through the slave SSPTXD. The slave receive logic performs serial to parallel conversion on the incoming
SSPRXD data stream, extracting and storing values into its receive FIFO, for subsequent reading through the APB
interface.
2.1.4 Enable SSP Operation
You can either prime the transmit FIFO, by writing up to eight 16-bit values when the PrimeCell SSP is disabled, or
allow the transmit FIFO service request to interrupt the CPU. Once enabled, transmission or reception of data
begins on the transmit (SSPTXD) and receive (SSPRXD) pins.
2.1.5 Transmit FIFO
The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. CPU data are stored
in the buffer until read out by the transmit logic.
When configured as a master or a slave parallel data is written into the transmit FIFO prior to serial conversion and
transmission to the attached slave or master respectively, through the SSPTXD.
2.1.6 Receive FIFO
The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data from
the serial interface are stored in the buffer until read out by the CPU.
When configured as a master or slave, serial data received through the SSPRXD is registered prior to parallel
loading into the attached slave or master receive FIFO respectively.