Samsung S3F401F - Manual (Page 227)

S3F401F_UM_REV1.00 TIMER
11-3
2. OPERATION DESCRIPTION
2.1 INTERVAL MODE OPERATION
In interval mode, a match signal should be generated when the counter value is identical to the value written to the
timer data register, TDATn. The match signal can generate a timer n match interrupt and auto-clear the counter
value.
If, for example, you write the value ‘0x10’ to TDATn, the counter will increment until it reaches ‘0x10’. At this point,
the Timer match interrupt (INT_TMCn) request is generated. And after the counter value is reset, count resumes.
With each match, the level of the signal at the TnPWM output pin is inverted, the period is equal to the t
CLK
*
(TDATA+1).
Match
Clear TCNT.15-.0: CV
16-Bit Counter
16-Bit Comparator
TDAT.15-.0: DATA
Timer Data Register
INTMASK
INTPND
TCON.1: IVT
TCLK
TCON.6: CL
Buffer Register
INT_TMCn
TnPWM
TCON.6: CL
Figure 11-2. Simplified Timer Function Diagram: Interval Timer Mode