Samsung S3F401F - Manual (Page 221)

SSP S3F401F_UM_REV1.00
10-20
Interrupt Mask Set /Clear Register SSPIMSC (0x014) Access: Read/Write
31 30 29 28 27 26 25 24
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
− − − −
TXIM RXIM RTIM RORIM
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset
RORIM Receive Overrun Interrupt Mask Bit
0 = RxFIFO written to while full condition interrupt is masked.
1 = RxFIFO written to while full condition interrupt is not masked.
RTIM Receive Timeout Interrupt Mask Bit
0 = RxFIFO not empty and no read prior to timeout period interrupt is masked.
1 = RxFIFO not empty and no read prior to timeout period interrupt is not masked.
RXIM Receive FIFO Interrupt Mask Bit
0 = Rx FIFO half full or less condition interrupt is masked.
1 = Rx FIFO half full or less condition interrupt is not masked.
TXIM Transmit FIFO Interrupt Mask Bit
0 = Tx FIFO half full or less condition interrupt is masked.
1 = Tx FIFO half full or less condition interrupt is not masked.
NOTE On a read this register gives the current value of the mask on the relevant interrupt. A write of 1 to the
particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask.