Samsung S3F401F - Manual (Page 215)

SSP S3F401F_UM_REV1.00
10-14
3. REGISTERS DESCRIPTION
Table 10-2. Clock & Power Management Special Function Register
Offset Address Register Description R/W Reset Value
0x000 SSPCR0 Control register 0 R/W 0x0000_0000
0x004 SSPCR1 Control register 1 R/W 0x0000_0010
Receive FIFO data register (READ) 0x008 SSPDR
Transmit FIFO data register (WRITE)
R/W 0x0000_0000
0x00C SSPSR Status register R 0x0000_0003
0x010 SSPCPSR Clock prescale register R/W 0x0000_0000
0x014 SSPIMSC Interrupt mask set and clear register R/W 0x0000_0000
0x018 SSPRIS Raw interrupt status register R 0x0000_0008
0x01C SSPMIS Masked interrupt status register R 0x0000_0000
0x020 SSPICR Interrupt clear register W 0x0000_0000
0x024
–
0xFDC
Reserved
− − −
0xFE0 SSPPeriphID0 Peripheral identification register bits7:0 R 0x0000_0022
0xFE4 SSPPeriphID1 Peripheral identification register bits15:8 R 0x0000_0010
0xFE8 SSPPeriphID2 Peripheral identification register bits23:16 R 0x0000_0004
0xFEC SSPPeriphID3 Peripheral identification register bits31:24 R 0x0000_0000
0xFF0 SSPPCellID0 PrimeCell identification register bits7:0 R 0x0000_000D
0xFF4 SSPPCellID1 PrimeCell identification register bits15:8 R 0x0000_00F0
0xFF8 SSPPCellID2 PrimeCell identification register bits23:16 R 0x0000_0005
0xFFC SSPPCellID3 PrimeCell identification register bits31:24 R 0x0000_00B1
NOTE: ID register’s read-only values tell the prime-cell ID information. (SSPPeriphID0/1/2/3, SSPPCellID0/1/2/3)
Base Address
− SSP0: 0xFF03_0000
− SSP1: 0xFF03_4000