Samsung S3F401F - Manual (Page 142)

INTERRUPT CONTROLLER S3F401F_UM_REV1.00
7-18
INTERRUPT OFFSET Register for IRQ INTOFFSIRQ (0x024) Access: Read/Write
31 30 29 28 27 26 25 24
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
−
INTOFFSIRQDAT [6:0]
R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after
reset
Each Interrupt Type Selection Bit INTOFFSIRQDAT
The value of this register represents the interrupt source number to be serviced which
was set to IRQ service in the INTMOD register. This register is set when the bit of
INTPND register is set to “1” and is cleared when the bit of INTPND register is set to “0”
Interrupt offset register for IRQ.
Indicates the interrupt offset address of interrupt source, which has the highest priority
among the pending interrupts.