Samsung S3F401F User Manual
Page 261
S3F401F_UM_REV1.00
UART
12-23
The maximum error using a 6-bit UARTTFBRD register = 1/64 x 100 = 1.56%. This occurs when m = 1, and the
error is cumulative over 64 clock ticks.
Next table shows some typical bit rates and their corresponding divisors, given the UART clock frequency of
7.3728MHz. These values do not use the fractional divider so the value in the UARTFBRD register is zero.
Programmed Integer Divisor
Bit rate (bps)
0x1 460800
0x2 230400
0x4 115200
0x6 76800
0x8 57600
0xC 38400
0x18 19200
0x20 14400
0x30 9600
0xC0 2400
0x180 1200
0x105D 110
Next table shows some required bit rates and their corresponding integer and fractional
divisor values and generated bit rates given a clock frequency of 4MHz.
Programmed divisor
(fraction)
Programmed divisor
(fraction)
Required bit
rate in bps
Generated bit
rate in bps
Error (%)
0x1 0x5
230400
231911
0.656
0x2 0xB
115200
115101
0.086
0x3 0x10
76800
76923
0.160
0x6 0x21
38400
38369
0.081
0x11 0x17
14400
14401
0.007
0x68 0xB
2400
2400
~
0
0x8E0 0x2F
110
110
~
0