Samsung S3F401F - Manual (Page 204)

S3F401F_UM_REV1.00 SSP
10-3
INTERFA
CE
RECEIVER
CLK_PRECALER
TRANSMITTER
DMA_INT_CON
B
u
s
C
on
trol
Signa
l
P
RDATA
PWDATA
PA
DDR
RXD
TXD
CONTROL
UNIT FSS
CLK
Figure 10-2. SUB Block Diagram
2.1 SSP FUNCTIONAL DESCRIPTION
2.1.1 Clock Prescaler
When configured as a master, an internal prescaler, comprising two free-running re-loadable serially linked counters,
is used to provide the serial output clock SSPCLK.
You can program the clock prescaler, through the SSPCPSR register, to divide PCLK by a factor of 2 to 254 in steps
of two. By not utilizing the least significant bit of the SSPCPSR register, division by an odd number is not possible
and this ensures a symmetrical (equal mark space ratio) clock is generated.
The output of the prescaler is further divided by a factor of 1 to 256, through the programming of the SSPCR0 control
register, to give the final master output clock SSPCLK.