Samsung S3F401F - Manual (Page 269)

S3F401F_UM_REV1.00 UART
12-31
UART Masked Interrupt Status Register UARTMIS (0x040) Access: Read Only
31 30 29 28 27 26 25 24
− − − − − − − −
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23 22 21 20 19 18 17 16
− − − − − − − −
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8
− − − − −
OEMIS BEMIS PEMIS
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7 6 5 4 3 2 1 0
FEMIS RTMIS TXMIS RXMIS
− − − −
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset
RXMIS Receive Masked Interrupt Status Bit
0: indicates UARTRXINTR interrupt is unmasked, enabled.
1: indicates UARTRXINTR interrupt is masked, disabled.
TXMIS Transmit Masked Interrupt Status Bit
0: indicates UARTTXINTR interrupt is unmasked, enabled.
1: indicates UARTTXINTR interrupt is masked, disabled.
RTMIS Receive Timeout Masked Interrupt Status Bit
0: indicates UARTRTINTR interrupt is unmasked, enabled.
1: indicates UARTRTINTR interrupt is masked, disabled.
FEMIS Framing Error Masked Interrupt Status Bit
0: indicates UARTFEINTR interrupt is unmasked, enabled.
1: indicates UARTFEINTR interrupt is masked, disabled.
PEMIS Parity Error Masked Interrupt Status Bit
0: indicates UARTPEINTR interrupt is unmasked, enabled.
1: indicates UARTPEINTR interrupt is masked, disabled.
BEMIS Break Error Masked Interrupt Status Bit
0: indicates UARTBEINTR interrupt is unmasked, enabled.
1: indicates UARTBEINTR interrupt is masked, disabled.
OEMIS Overrun Error Masked Interrupt Status Bit
0: indicates UARTOEINTR interrupt is unmasked, enabled.
1: indicates UARTOEINTR interrupt is masked, disabled.