Samsung S3F401F - Manual (Page 208)

S3F401F_UM_REV1.00 SSP
10-7
2.2.1 SSP format with SPO=0, SPH=0
Single and continuous transmission signal sequences for SSP format with SPO=0, SPH=0 are shown in below
figure.
4 to 16 bits
SSPCLK
SSPFSS
SSPRXD Q LSB MSB
LSB MSB
SSPTXD
Figure 10-3. SSP frame format (single transfer) with SPO=0 and SPH=0
MSB LSB
4 to 16 bits
SSPCLK
SSPFSS
SSPTXD/
SSPRXD
MSB LSB
Figure 10-4. SSP frame format (continuous transfer) with SPO=0 and SPH=0
In this configuration, during idle periods:
• The SSPCLK signal is forced LOW
• SSPFSS is forced HIGH
• The transmit data line SSPTXD is arbitrarily forced LOW
• When the PrimeCell SSP is configured as a master, the SSPCLK is enabled.
• When the PrimeCell SSP is configured as a slave, SSPCLK is disabled.
If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the
SSPFSS master signal being driven LOW. This causes slave data to be enabled onto the SSPRXD input line of the
master.
One half SSPCLK period later, valid master data is transferred to the SSPTXD pin. Now that both the master and
slave data have been set, the SSPCLK master clock pin goes HIGH after one further half SSPCLK period.
The data is now captured on the rising and propagated on the falling edges of the SSPCLK signal.