Samsung S3F401F - Manual (Page 13)

x S3F401F_UM_REV1.00 MICROCONTROLLER
List of Figures
(Continued)
Figure Title Page
Number Number
10-1 SSP Block Diagram ..................................................................................................... 10-2
10-2 SUB Block Diagram..................................................................................................... 10-3
10-3 SSP frame format (single transfer) with SPO=0 and SPH=0...................................... 10-7
10-4 SSP frame format (continuous transfer) with SPO=0 and SPH=0.............................. 10-7
10-5 SSP frame format with SPO=0 and SPH=1 ................................................................ 10-8
10-6 SSP frame format (single transfer) with SPO=1 and SPH=0...................................... 10-9
10-7 SSP frame format (continuous transfer) with SPO=1 and SPH=0.............................. 10-9
10-8 SSP Frame Format with SPO=1 and SPH=1.............................................................. 10-10
10-9 PrimeCell SSP Master Coupled to Two Slaves .......................................................... 10-11
10-10 SPI master coupled to two PrimeCell SSP slaves ...................................................... 10-12
11-1
16-Bit Timer Block Diagram ........................................................................................ 11-2
11-2 Simplified Timer Function Diagram: Interval Timer Mode ........................................... 11-3
11-3 Simplified Timer Function Diagram: Match & Overflow Timer Mode .......................... 11-4
11-4 Simplified Timer Function Diagram: Capture Mode .................................................... 11-5
11-5 Simplified Timer Function Diagram: PWM Mode ........................................................ 11-6
11-6 PWM Signal Generation Diagram ............................................................................... 11-7
12-1
UART Block Diagram (with FIFO) ............................................................................... 12-5
12-2 UART character frame ................................................................................................ 12-7
12-3 IrDA data modulation................................................................................................... 12-10
13-1
ADC Offset Error ......................................................................................................... 13-6
13-2 ADC DLE, ILE.............................................................................................................. 13-7
14-1
100-QFP-1420 Package Dimensions.......................................................................... 14-1