Samsung S3F401F - Manual (Page 252)

UART S3F401F_UM_REV1.00
12-14
4. REGISTERS DESCRIPTION
Table 12-1. UART Special Function Registers
Offset Address Register Description R/W Reset Value
0x000 UARTDR Data register R/W Undefined
0x004 UARTRSR Receive status register/error clear register R/W 0x0000_0000
0x008
−
0x014
Reserved Reserved
− −
0x018 UARTFR Flag register R 0x0000_0090
0x01C Reserved Reserved
− −
0x020 UARTILPR IrDA low power counter register R/W 0x0000_0000
0x024 UARTIBRD Integer baud rate register R/W 0x0000_0008
0x028 UARTFBRD Funcational baud rate register R/W 0x0000_0000
0x02C UARTLCR_H Line control register R/W 0x0000_0000
0x030 UARTCR Control register R/W 0x0000_0300
0x034 UARTIFLS Interrupt FIFO level select register R/W 0x0000_0012
0x038 UARTIMSC Interrupt mask set / clear register R/W 0x0000_0000
0x03C UARTRIS Raw interrupt status register R 0x0000_0000
0x040 UARTMIS Masked interrupt status register R 0x0000_0000
0x044 UARTICR Interrupt clear register W 0x0000_0000
0x048
−
0xFDC
Reserved Reserved
− −
0xFE0 UARTPeriphID0 Peripheral ID register bits7:0 R 0x0000_0011
0xFE4 UARTPeriphID1 Peripheral ID register bits15:8 R 0x0000_0010
0xFE8 UARTPeriphID2 Peripheral ID register bits23:16 R 0x0000_0024
0xFEC UARTPeriphID3 Peripheral ID register bits31:24 R 0x0000_0000
0xFF0 UARTPCellID0 PrimeCell ID register bits7:0 R 0x0000_000D
0xFF4 UARTPCellID1 PrimeCell ID register bits15:8 R 0x0000_00F0
0xFF8 UARTPCellID2 PrimeCell ID register bits23:16 R 0x0000_0005
0xFFC UARTPCellID3 PrimeCell ID register bits31:24 R 0x0000_00B1
NOTE: ID register’s read-only values tell the prime-cell ID information.(UARTPeriphID0/1/2/3, UARTCellID0/1/2/3)
Base Address
− UART0: 0xFF03_8000
– UART1: 0xFF03_C000