Samsung S3F401F - Manual (Page 239)

S3F401F_UM_REV1.00 UART
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UART
1. OVERVIEW
The S3F401F has two UART serial communication interface using the prime-cell PL011 of ARM. The S3F401F
UART includes programmable baud rates, infra-red (IR) transmit/receive, one or two stop-bit insertion, 5-bit, 6-bit,
7-bit or 8-bit data width and parity checking.
1.1 THE UART PERFORMS:
• Serial-to-parallel conversion on data received from a peripheral device
• Parallel-to-serial conversion on data transmitted to the peripheral device.
The UART:
• Includes a programmable baud rate generator that generates a common transmit and receive internal clock
from the UART internal reference clock input, PCLK
• Supports baud rates of up to 460.8Kbits/s, subject to PCLK reference clock frequency
The UART operation and baud rate values are controlled by the line control register (UARTLCR_H) and the baud
rate divisor registers (UARTIBRD and UARTFBRD).
The UART can generate:
• Individually maskable interrupts from the receive (including timeout), transmit and error conditions
• A single combined interrupt so that the output is asserted if any of the individual interrupts are asserted, and
unmasked
If a framing, parity, or break error occurs during reception, the appropriate error bit is set, and is stored in the
FIFO. If an overrun condition occurs, the overrun register bit is set immediately and FIFO data is prevented from
being overwritten.
You can program the FIFOs to be 1-byte deep providing a conventional double-buffered