Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 54)

44 Direct I/O Models
designated I/O pin. This I/O pin is operated as an open-drain device in order to
support the interface.
Up to 255 bytes of data can be transferred at a time.
For more information about this protocol, and the devices that it supports, see
application note 937, Book of iButton Standards , from Maxim Integrated
Products.
This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to
Series 5000 Neuron Processors and Smart Transceivers.
Hardware Considerations
Up to eight 1-Wire memory busses can be connected to a Smart Transceiver
through the use of the first eight I/O pins, IO0 – IO7. The only additional
component required for this is a pull-up resistor on the data line (refer to the 1-
Wire Memory specification below on how to select the value of the pull-up
resistor). The high current sink capabilities of IO0 – IO3 pins of a Series 3100
Smart Transceiver can be used in applications where long wire lengths are
required between the 1-Wire device and the Smart Transceiver.
The slave acquires all necessary power for its operation from the data line. Upon
physical connection of a 1-Wire device to a master (in this case the Smart
Transceiver), the 1-Wire Memory generates a low presence pulse to inform the
master that it is awaiting a command. The Smart Transceiver can also request a
presence pulse by sending a reset pulse to the 1-Wire device.
Commands and data are sent bit by bit to make bytes, starting with the least-
significant bit (LSB). The synchronization between the Smart Transceiver and
the 1-Wire devices is accomplished through a negative-going pulse generated by
the Smart Transceiver.
Figure 17 on page 45 shows the details of the reset pulse in addition to the
read/write bit slots.
Note: NodeBuilder 3.1 and Mini EVK, or later, both feature the ability to adjust
the t
low
, t
wrd
, and t
rdi
timing values.