beautypg.com

Figure 64 on – Echelon I/O Model Reference for Smart Transceivers and Neuron Chips User Manual

Page 182

background image

172

Timer/Counter Output Models

• If the output is disabled, the new (non-zero) output starts immediately

after t

fout

• For a new output value of zero, the output is disabled immediately and

not at the end of the current cycle

A disabled output is a logic 0 by default, unless the invert keyword is used in the

I/O object declaration.

ONE CYCLE

NEW OUTPUT

APPEARS ON PIN

HARDWARE

UPDATED

INTERNALLY

START

OF

io_out()

ONE CYCLE

TIME

PULSEWIDTH

OUTPUT

t

fout

t

ret

Timer/Counter 1

Timer/Counter 2

IO10

IO9

IO8

IO0

IO1
IO2

IO3
IO4

IO5
IO6

IO7

High Current Sink Drivers for 3100 Family Devices

IO11

System Clock

Divide Chain

Figure 64. Pulsewidth Output and Timing

Table 64. Pulsewidth Output Latency Values for Series 3100 Devices

Symbol

Description

Typical at 10 MHz

t

fout

Function call to output update

101 μs

t

ret

Return from function

13 μs