Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 50)

40 Direct I/O Models
independently from I/O objects, and can be triggered by positive or negative level,
rising or falling edge, or either edge of the I/O signal (regardless of the I/O
object’s direction), I/O interrupts can often be used in place of a leveldetect object.
For Series 3100 devices, add a #pragma enable_io_pullups directive to enable the
Neuron Chip's or Smart Transceiver's built-in pull-up resistors on pins IO_4
through IO_7.
Syntax
pin [input] leveldetect io-object-name ;
pin
An I/O pin. Leveldetect input can specify one of the pins IO_0 through IO_7.
io-object-name
A user-specified name for the I/O object, in the ANSI C format for variable
identifiers.
Usage
unsigned int input-value ;
input-value = io_in( io-object-name );
Example
IO_6 input leveldetect ioGrounded;
when (io_changes(ioGrounded) to TRUE) {
...
// this task runs when I/0 reaches logical 0 level
}
Nibble Input/Output
The nibble I/O model is used to read or control four adjacent pins simultaneously.
This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to
Series 5000 Neuron Processors and Smart Transceivers.
Hardware Considerations
Groups of four consecutive pins between IO0 – IO7 can be configured as nibble-
wide (4-bit) input or output ports, which can be read or written to using integers
in the range 0 to 15. This model is useful for reading or writing a synchronized
process image, where multiple binary outputs are assigned (or sampled)
simultaneously. Other uses include driving devices that require binary-coded
decimal (BCD) data, or other data four bits at a time. For example, a 4x4 key
switch matrix can be scanned by using one nibble to generate an output (row
select — one of four rows), and one nibble to read the input from the columns of
the switch matrix.