Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 169)

I/O Model Reference 159
Example
IO_0 output edgedivide sync(IO_4) ioDivider;
...
when (reset) {
// There is a 60Hz signal at pin IO_4.
// Set up the divider to produce
// a change on pin IO_0 once a minute.
io_out(ioDivider, 3600UL);
}
Frequency Output
For Series 3100 devices, the frequency I/O model produces a repeating square
wave output signal whose period is a function of output_value and the selected
clock value:
period (ns) = (output_value+n) * 4000 * 2^(clock)/ input_clock (MHz)
where clock ranges from 0..7, and n = 1 for clock(0) or n = 0 otherwise.
For Series 5000 devices, the frequency I/O model produces a repeating square
wave output signal whose period is a function of output_value and the selected
clock value:
period (ns) = (output_value+n) * 4000 * 2^(value)/ 10 MHz
where value ranges from 0..15, and n = 1 for clock(0) or n = 0 otherwise.
You can use this I/O model for frequency synthesis to drive an audio transducer
or to drive a frequency-to-voltage converter to generate an analog output.
This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to
Series 5000 Neuron Processors and Smart Transceivers.
Hardware Considerations
A timer/counter can be configured to generate a continuous square wave of 50%
duty cycle. Writing a new frequency value to the device takes effect at the end of
the current cycle. This object is useful for frequency synthesis to drive an audio
transducer, or to drive a frequency to voltage converter to generate an analog
output (see Figure 59 and Figure 60 on page 160).
The resolution and range of the timer/counter period options is described in
Timer/Counter Resolution and Maximum Range on page 188.
A new frequency output value does not take effect until the end of the current
cycle, with two exceptions:
• If the output is disabled, the new (non-zero) output starts immediately
after t
fout
• For a new output value of zero, the output is disabled immediately and
not at the end of the current cycle
A disabled output is a logic zero by default unless the invert keyword is used in
the I/O object declaration. The resolution and range for this object scale with
Neuron Chip or Smart Transceiver input clock rate.