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Scheduler-related i/o timing information – Echelon I/O Model Reference for Smart Transceivers and Neuron Chips User Manual

Page 23

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I/O Model Reference

13

page 107 for more information. Also, for Series 5000 devices, when hardware

interrupt tasks run in the application (APP) processor (for the two lowest clock
rates), the contribution of interrupt processing, including the application-specific

interrupt tasks, directly adds to the scheduler delay. However, at higher clock

rates, the contribution of interrupts is very small and approximately constant.

Scheduler-Related I/O Timing Information

As part of the Neuron system firmware, the scheduler provides an orderly and

predictable means to facilitate the evaluation of user-defined events. The when

clause, provided by the Neuron C language, is used to specify such events. For
more information on the operation of the scheduler, see the

Neuron C

Programmer’s Guide.

There is a finite latency associated with the operation of the scheduler. The time

required for the scheduler to evaluate the same when

clause in a particular user

application program is, to a large extent, a function of the size of the user code,
the total number of when clauses, and the state of the events associated with

those when

clauses. Therefore, it is impractical to specify a nominal value for

this latency, because each application has its own distinct behavior.

The best-case latency can be viewed in several ways, each exposing a different

aspect of the operation of the scheduler. A simple example consists of having an

application program that consists of two when

clauses, both of which always

evaluate to TRUE, as shown below.

IO_0 output bit testbit;

when (TRUE) {
io_out (testbit, 1);
}

when (TRUE) {
io_out (testbit, 0);
}

Processing of when clauses is performed in a round-robin fashion; therefore, the
Neuron C code above performs alternating activation of the IO0 pin (in this case,

to isolate and extract the timing parameters associated with the scheduler). The

waveform seen on pin IO0 of the device, as a result of the above code, is shown in

Figure 5 on page 14.