Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 106)

96 Serial I/O Models
5. When the input clock is low, return to step 1 if there are more bits to be
processed.
6. Else return the number of bits processed.
When either clock input test fails (that is, the clock is sampled before the next
transition), there is an additional timeout check time of 19.8 μs (wait for clock
high) or 19.2 μs (wait for clock low) added to that stage of the algorithm.
The chip select logic for the Neurowire slave can be handled by the user through
a separate bit input object, along with an appropriate handshaking algorithm
implemented by the user application program. To prevent unnecessary timeouts,
the setup and hold times of the chip select line, relative to the start and end of
the external clock, must be satisfied.
The timeout input pin can either be connected to an external timer or to an
output pin of the Smart Transceiver that is declared as a oneshot object.
Programming Considerations
The Neurowire I/O object can be configured in master mode or slave mode. The
primary difference between master and slave modes is that the clock signal is an
output for the master mode, and an input for the slave mode. Data is shifted in
at the same time as data is shifted out.
In Neurowire master mode, one or more of the pins IO_0 through IO_7 can be
used as a chip select, allowing multiple Neurowire devices to be connected on a 3-
wire bus. The clock rate can be specified as 1, 10, or 20 kbps for a Series 3100
Neuron Chip or Smart Transceiver with an input clock rate of 10 MHz, or as 16,
160, or 320 kbps for a Series 5000 device with an input clock of 80 MHz; these
scale proportionally with input clock.
In Neurowire slave mode, one of the IO_0 through IO_7 pins can be designated as
a timeout pin. A logic one level on the timeout pin causes the Neurowire slave
I/O operation to be terminated before the specified number of bits has been
transferred. This prevents the Neuron Chip or Smart Transceiver watchdog
timer from resetting the chip in the event that fewer than the requested number
of bits are transferred by the external clock.
In both master and slave modes, up to 255 bits of data can be transferred at a
time. Neurowire I/O suspends application processing until the operation is
complete.
For Neurowire input/output, the io_in( ) and io_out( ) functions require a pointer
to the data buffer as the input_value and output_value. Because Neurowire I/O
is bidirectional, input and output occur at the same time, and therefore, the calls
io_in( ) and io_out( ) are equivalent. Use of either call initiates a bidirectional
transfer. Data is transmitted 8 bits at a time, most significant bit first. The
clock edge used to clock the data is specified by the clockedge parameter. Data is
also then transferred into the same buffer pointed to by input_value or
output_value, most significant bit first, following the clock edge, overwriting the
original contents of the buffer. If the number of bits to be transferred is not a
factor of eight as defined by
count , the last byte transferred into the buffer will
contain undefined data bit values in the remaining (unfilled) bit locations.
When using multiple serial or Neurowire I/O objects that have differing bit rates,
the following compiler directive must be used: #pragma enable_multiple_baud.