Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 42)

32 Direct I/O Models
Bit Input/Output
The bit I/O model is used to read or control the logical state of a single pin, where
0 represents low and 1 represents high.
This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to
Series 5000 Neuron Processors and Smart Transceivers.
Hardware Considerations
Pins IO0 – IO11 can be individually configured as single-bit input or output
ports. Inputs can be used to sense transistor-transistor logic (TTL)-level
compatible logic signals from external logic, contact closures, and so on. Outputs
can be used to drive external CMOS and TTL-level compatible logic, switch
transistors, and very low current relays to actuate higher-current external
devices such as stepper motors and lights.
For Series 3100 devices, the high (20 mA) current sink capability of pins IO0 –
IO3 (see Figure 7) allows these pins to drive many I/O devices directly.
IO10
IO9
IO8
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
High Current Sink Drivers Optional Pull-Up Re-
sistors
IO10
IO9
IO8
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO11 IO11
Figure 7. Bit I/O for Series 3100 Devices
Notes:
• After a reset, a Series 3100 power line device disables the IO4-IO7 and
IO11 pull-up resistors. The pull-up resistors are not turned on until
application initialization. Pull-ups are only enabled when specified in the
application configuration using the #pragma enable_io_pullups Neuron C
directive.
• After a reset, a Series 3100 FT device performs a self test, which includes
enabling the IO4-IO7 pull-up resistors. Enabling the pull-up resistors
could cause a positive transition on the pins.
Figure 8 on page 33 and Figure 9 on page 33 show the bit input and bit output
latency times, respectively. These are the times from the call to the io_in() or
io_out() function, until a value is returned. The direction of bit ports can be
changed between input and output dynamically by using the io_set_direction()
function.