Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 136)

126 Timer/Counter Input Models
the input clock). Faster conversion rates are attainable at the expense of bit
resolution.
For a Series 3100 device, the duration of the first integration period is a function
of control_value and the selected clock value:
duration (ns) = control_value * 2000 * 2^(clock) / input_clock (MHz)
where clock ranges from 0..7
For a Series 5000 device, the duration of the first integration period is a function
of control_value and the selected clock value:
duration (ns) = control_value * 2000 * 2^(value) / 10 MHz
where value ranges from 0..15
For a Series 3100 device, the value read back by this device reflects the length of
the second integration period, and is also in units of the selected clock value:
2nd_integration (ns) = input_value * 2000 * 2^(clock) / input_clock (MHz)
where clock ranges from 0..7
For a Series 5000 device, the value read back by this device reflects the length of
the second integration period, and is also in units of the selected clock value:
2nd_integration (ns) = input_value * 2000 * 2^(value) / 10 MHz
where value ranges from 0..15
A single timer/counter provides the control out signal and senses a comparator
output signal. The control output signal controls an external analog multiplexer
that switches between the unknown input voltage and a voltage reference. The
timer/counter’s input pin is driven by an external comparator that compares an
integrator output with a voltage reference.
This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to
Series 5000 Neuron Processors and Smart Transceivers.
Hardware Considerations
The timer/counter provides the control output signal, and senses a comparator
output signal. The control output signal controls an external analog multiplexer
that switches between the unknown input voltage and a voltage reference. The
timer/counter’s input pin is driven by an external comparator that compares the
integrator’s output with a voltage reference. At the end of conversion, the
external comparator drives a low level to one of pins IO4 – IO7. If external
circuitry indicates “end of conversion” with a high level, use the invert keyword
in the I/O object’s declaration.
The resolution and range of the timer/counter period options is described in
Timer/Counter Resolution and Maximum Range on page 188.