Maxim Integrated MAX31782 User Manual
Maxim Integrated Hardware
Table of contents
Document Outline
- TABLE OF CONTENTS
- SECTION 1: Overview
- SECTION 2: Architecture
- SECTION 3: System Register Descriptions
- 3.1 System Register Bit Descriptions
- 3.1.1 Accumulator Pointer Register (AP, 8h[0h])
- 3.1.2 Accumulator Pointer Control Register (APC, 8h[1h])
- 3.1.3 Processor Status Flags Register (PSF, 8h[4h])
- 3.1.4 Interrupt and Control Register (IC, 8h[5h])
- 3.1.5 Interrupt Mask Register (IMR, 8h[6h])
- 3.1.6 System Control Register (SC, 8h[8h])
- 3.1.7 Interrupt Identification Register (IIR, 8h[Bh])
- 3.1.8 System Clock Control Register (CKCN, 8h[Eh])
- 3.1.9 Watchdog Control Register (WDCN, 8h[Fh])
- 3.1.10 Accumulator n Register (A[n], 9h[nh])
- 3.1.11 Prefix Register (PFX[n], Bh[n])
- 3.1.12 Instruction Pointer Register (IP, Ch[0h])
- 3.1.13 Stack Pointer Register (SP, Dh[1h])
- 3.1.14 Interrupt Vector Register (IV, Dh[2h])
- 3.1.15 Loop Counter 0 Register (LC[0], Dh[6h])
- 3.1.16 Loop Counter 1 Register (LC[1], Dh[7h])
- 3.1.17 Frame Pointer Offset Register (OFFS, Eh[3h])
- 3.1.18 Data Pointer Control Register (DPC, Eh[4h])
- 3.1.19 General Register (GR, Eh[5h])
- 3.1.20 General Register Low Byte (GRL, Eh[6h])
- 3.1.21 Frame Pointer Base Register (BP, Eh[7h])
- 3.1.22 General Register Byte-Swapped (GRS, Eh[8h])
- 3.1.23 General Register High Byte (GRH, Eh[9h])
- 3.1.24 General Register Sign Extended Low Byte (GRXL, Eh[Ah])
- 3.1.25 Frame Pointer Register (FP, Eh[Bh])
- 3.1.26 Data Pointer 0 Register (DP[0], Fh[3h])
- 3.1.27 Data Pointer 1 Register (DP[1], Fh[7h])
- 3.1 System Register Bit Descriptions
- SECTION 4: Peripheral Register Modules
- SECTION 5: Interrupts
- 5.1 Servicing Interrupts
- 5.2 Module Interrupt Identification Registers
- 5.2.1 Peripheral Module 0 Interrupt Identification Register (MIIR0, M0[03h])
- 5.2.2 Peripheral Module 1 Interrupt Identification Register (MIIR1, M1[04h])
- 5.2.3 Peripheral Module 2 Interrupt Identification Register (MIIR2, M2[03h])
- 5.2.4 Peripheral Module 3 Interrupt Identification Register (MIIR3, M3[10h])
- 5.2.5 Peripheral Module 4 Interrupt Identification Register (MIIR4, M4[10h])
- 5.2.6 Peripheral Module 5 Interrupt Identification Register (MIIR5, M5[18h])
- 5.3 Interrupt System Operation
- SECTION 6: Analog-to-Digital Converter (ADC)
- 6.1 Detailed Description
- 6.2 ADC Register Descriptions
- 6.2.1 ADC Control Register (ADCN)
- 6.2.2 ADC Status Register (ADST)
- 6.2.3 ADC Address Register (ADADDR)
- 6.2.4 ADC Data and Configuration Register (ADDATA)
- 6.2.5 External Temperature Slope Control Register (ETS)
- 6.2.6 ADC External Temperature Offset Register (TOEX)
- 6.2.7 ADC Voltage Offset Register (ADVOFF)
- 6.2.8 ADC Voltage Scale Trim Registers (ADCG1 and ADCG5)
- 6.3 ADC Code Examples
- SECTION 7: I2C-Compatible Slave Interface
- 7.1 Detailed Description
- 7.2 I2C Slave Controller Register Descriptions
- 7.2.1 I2C Slave Control Register (I2CCN_S)
- 7.2.2 I2C Slave Status Register (I2CST_S)
- 7.2.3 I2C Slave Interrupt Enable Register (I2CIE_S)
- 7.2.4 I2C Slave Address Register (I2CSLA_S)
- 7.2.5 I2C Slave Data Buffer Register (I2CBUF_S)
- 7.2.6 SMBus Mode Selection Register (SMBUS)
- 7.2.7 I2C Slave Clock Control Register (I2CCK_S)
- 7.2.8 I2C Slave Timeout Register (I2CTO_S)
- SECTION 8: I2C-Compatible Master Interface
- 8.1 Detailed Description
- 8.1.1 Description of Master I2C Interface
- 8.1.2 Default Operation
- 8.1.3 I2C Clock Generation
- 8.1.4 Timeout
- 8.1.5 Generating a START
- 8.1.6 Generating a STOP
- 8.1.7 Transmitting a Slave Address
- 8.1.8 Transmitting Data
- 8.1.9 Receiving Data
- 8.1.10 I2C Master Clock Stretching
- 8.1.11 Resetting the I2C Master Controller
- 8.1.12 Operation as a Slave
- 8.1.13 GPIO
- 8.2 I2C Master Controller Register Descriptions
- 8.2.1 I2C Master Control Register (I2CCN_M)
- 8.2.2 I2C Master Status Register (I2CST_M)
- 8.2.3 I2C Master Interrupt Enable Register (I2CIE_M)
- 8.2.4 I2C Master Data Buffer Register (I2CBUF_M)
- 8.2.5 I2C Master Clock Control Register (I2CCK_M)
- 8.2.6 I2C Master Timeout Register (I2CTO_M)
- 8.2.7 I2C Master Address Register (I2CSLA_M)
- 8.2.8 SMBus Mode Selection Register (SMBUS)
- 8.1 Detailed Description
- SECTION 9: PWM Outputs
- SECTION 10: Fan Tachometer
- SECTION 11: General-Purpose Input/Output (GPIO) Pins
- 11.1 GPIO Port 1 Register Descriptions
- 11.2 GPIO Port 2 Register Descriptions
- 11.3 GPIO Port 6 Register Descriptions
- 11.3.1 GPIO Direction Register Port 6 (PD6)
- 11.3.2 GPIO Output Register Port 6 (PO6)
- 11.3.3 GPIO Input Register for Port 6 (PI6)
- 11.3.4 GPIO Port 6 External Interrupt Edge Select Register (EIES6)
- 11.3.5 GPIO Port 6 External Interrupt Flag Register (EIF6)
- 11.3.6 GPIO Port 6 External Interrupt Enable Register (EIE6)
- 11.4 GPIO Code Example
- SECTION 12: Timer B Module
- SECTION 13: Supply Voltage Monitor
- SECTION 14: Hardware Multiplier
- 14.1 Hardware Multiplier Organization
- 14.2 Hardware Multiplier Controls
- 14.3 Register Output Selection
- 14.4 Hardware Multiplier Operations
- 14.5 Hardware Multiplier Peripheral Registers
- 14.5.1 Multiplier Control Register (MCNT)
- 14.5.2 Multiplier Operand A Register (MA)
- 14.5.3 Multiplier Operand B Register (MB)
- 14.5.4 Multiplier Accumulator 2 Register (MC2)
- 14.5.5 Multiplier Accumulator 1 Register (MC1)
- 14.5.6 Multiplier Accumulator 0 Register (MC0)
- 14.5.7 Multiplier Read Register 1 (MC1R)
- 14.5.8 Multiplier Read Register 0 (MC0R)
- 14.6 Hardware Multiplier Examples
- SECTION 15: Watchdog Timer
- SECTION 16: Test Access Port (TAP)
- SECTION 17: In-Circuit Debug Mode
- 17.1 Background Mode Operation
- 17.2 Debug Mode
- 17.3 In-Circuit Debug Peripheral Registers
- 17.3.1 In-Circuit Debug Temp 0 Register (ICDT0, M2[18h])
- 17.3.2 In-Circuit Debug Temp 1 Register (ICDT1, M2[19h])
- 17.3.3 In-Circuit Debug Control Register (ICDC, M2[1Ah])
- 17.3.4 In-Circuit Debug Flag Register (ICDF, M2[1Bh])
- 17.3.5 In-Circuit Debug Buffer Register (ICDB, M2[1Ch])
- 17.3.6 In-Circuit Debug Address Register (ICDA, M2[1Dh])
- 17.3.7 In-Circuit Debug Data Register (ICDD, M2[1Eh])
- SECTION 18: In-System Programming
- 18.1 Detailed Description
- 18.2 Bootloader Operation
- 18.3 Bootloader Commands
- 18.3.1 Command 00h—No Operation
- 18.3.2 Command 01h—Exit Loader
- 18.3.3 Command 02h—Master Erase
- 18.3.4 Command 03h—Password Match
- 18.3.5 Command 04h—Get Status
- 18.3.6 Command 05h—Get Supported Commands
- 18.3.7 Command 06h—Get Code Size
- 18.3.8 Command 07h—Get Data Size
- 18.3.9 Command 08h—Get Loader Version
- 18.3.10 Command 09h—Get Utility ROM Version
- 18.3.11 Command 0Eh—Get Device Number
- 18.3.12 Command 10h—Load Code
- 18.3.13 Command 11h—Load Data
- 18.3.14 Command 20h—Dump Code
- 18.3.15 Command 21h—Dump Data
- 18.3.16 Command 30h—CRC Code
- 18.3.17 Command 31h—CRC Data
- 18.3.18 Command 40h—Verify Code
- 18.3.19 Command 41h—Verify Data
- 18.3.20 Command 50h—Load and Verify Code
- 18.3.21 Command 51h—Load and Verify Data
- 18.3.22 Command E0h—Code Page Erase
- SECTION 19: Programming
- 19.1 Addressing Modes
- 19.2 Prefixing Operations
- 19.3 Reading and Writing Registers
- 19.4 Reading and Writing Register Bits
- 19.5 Using the Arithmetic and Logic Unit
- 19.5.1 Selecting the Active Accumulator
- 19.5.2 Enabling Auto-Increment and Auto-Decrement
- 19.5.3 ALU Operations Using the Active Accumulator and a Source
- 19.5.4 ALU Operations Using Only the Active Accumulator
- 19.5.5 ALU Bit Operations Using Only the Active Accumulator
- 19.5.6 Example: Adding Two 4-Byte Numbers Using Auto-Increment
- 9.6 Processor Status Flag Operations
- 19.7 Controlling Program Flow
- 19.8 Handling Interrupts
- 19.9 Accessing the Stack
- 19.10 Accessing Data Memory
- SECTION 20: Instruction Set Summary
- SECTION 21: Utility ROM
- REVISION HISTORY