9 smbus timeout, 10 resetting the i2c slave controller, 11 operation as a master – Maxim Integrated MAX31782 User Manual
Page 63: 12 gpio, 7 .1 .9 smbus timeout -7 7 .1 .10 resetting the i, C slave controller -7, 7 .1 .11 operation as a master -7 7 .1 .12 gpio -7, 9smbustimeout, 10resettingthei, Cslavecontroller
MaximIntegrated 7-7
MAX31782 User’s Guide
Revision 0; 8/11
7.1.9SMBusTimeout
The I
2
C slave controller can also be used for SMBus or PMBus™ communication . To maintain SMBus compatibility, a
30ms timer is implemented by the I
2
C slave controller . The purpose of this timer is to issue a timeout interrupt when SCL
is low for greater than 30ms . The timer only starts when none of the following conditions are true:
1) The I
2
C slave controller is in the idle state and there is no communications on the I
2
C bus . The timer should not
generate interrupts if the I
2
C slave controller is in the idle state regardless of how long SCL is low .
2) The SMBus mode bit is not set . This ensures the SMBus timeout functionality does not interfere with normal I
2
C
functionality .
3) SCL is high . The timer is inactive whenever SCL is high . The timer resets when it is inactive .
4) The I
2
C slave controller is disabled or used as a master I
2
C controller . The timer is not needed in this case .
The following description explains when the SMBus timer starts, assuming that all other START conditions are met .
When the MAX31782’s I
2
C slave controller is idle and it receives a START, it exits the idle state and the timer becomes
active (starts counting) any time SCL goes low . If following the START the master addresses a different slave on the
bus, the I
2
C slave controller returns to the idle state and the timer is reset and becomes inactive . In short, as soon as
SCL goes low following a START, the SMBus timer becomes active until the I
2
C slave controller re-enters idle state .
When a timeout occurs, the timeout bit (I2CTOI) is set, which can generate an interrupt if enabled . If a timeout occurs,
it may be necessary to reset the I
2
C slave controller . See
for more details .
SMBus mode selection is controlled by the SMBUS register . When the slave SMBus mode operation bit (SMB_MOD_S)
is set to 1, the SMBus timeout functionality is enabled .
7.1.10ResettingtheI
2
CSlaveController
The I
2
C slave controller can be reset by setting the RESET_S bit in the SMBUS register . After a delay of at least one
system clock, this bit needs to be cleared to 0 by software and the reset is complete . A reset forces the I
2
C slave
controller to release both SDA and SCL if they are being held low by the I
2
C slave controller . The reset also turns off
the I
2
C slave controller (I2CEN = 0), resets all the I
2
C registers, and resets the internal state machine of the I
2
C slave
controller . Following a reset, the I
2
C slave controller must be reinitialized, including enabled (I2CEN = 1) before it can
be used again .
7.1.11OperationasaMaster
The MAX31782 contains two I
2
C interfaces, the slave (SDA and SCL) and master (MSDA and MSCL) . These are two
totally separate blocks within the MAX31782 . However, both of the blocks are identical . Because of this, it is possible
to operate the slave as a master and also operate the master as a slave .
To operate the slave (SDA and SCL) as a master I
2
C interface, the I2CMST bit in I2CCN_S needs to be set to a 1 .
When the slave is operating as a master, it uses the same registers (I2CCN_S, I2CST_S, etc) that it uses for slave
operation . However, the bits in these registers have different functionality, as described in
. The SMBUS .RESET_S bit can still be used to reset this interface (SDA and SCL) when operating as a
master . The SMBUS .SMB_MOD_S bit has no effect when the interface is operating in master mode . See
for details on initializing and using a master I
2
C interface .
Note:WhentheI
2
Cslaveinterfaceischangedtooperateinmastermode,theI
2
Cbootloaderisnotavailable.
7.1.12GPIO
When the I
2
C slave controller is disabled (I2CCN_S .I2CEN = 0), the SDA and SCL pins can be used as GPIO pins . The
SDA pin is mapped to GPIO port P6 .7 and SCL is mapped to GPIO port P6 .6 . When used as GPIO outputs, the SDA
and SCL pins can only be open-drain outputs . See
SECTION 11: General-Purpose Input/Output (GPIO) Pins
information on using SDA and SCL as GPIO pins .
Note:WhentheI
2
Cslaveinterfaceisdisabled,theI
2
Cbootloaderisnotavailable.
PMBus is a trademark of SMIF, Inc.