Maxim Integrated MAX31782 - Manual (Page 147)

MaximIntegrated 17-12
MAX31782 User’s Guide
Revision 0; 8/11
Note that the trace operation uses a return address from the stack as a legitimate address for program fetching . The
host must maintain consistency of program flow during the debug process . The Instruction Pointer is automatically
incremented after each trace operation, thus a new return address is pushed onto the stack before returning the control
to the debug engine . Also, note that the interrupt handler is an essential part of the CPU and a pending interrupt could
be granted during single-step operation since the IGE bit state present on debug mode entry is restored for the single
step .
17.2.4Return
To terminate the debug mode and return the debug engine to background mode, the host must issue a Return com-
mand to the debug engine . This command causes the following actions:
1) Pop the return address from the stack .
2) Set the IGE bit to logic 1 if debug mode was activated when IGE = 1 .
3) Supply the CPU with an instruction addressed by the return address .
4) Allow the CPU to execute the normal user program .
5) Set the status to 00b (non-debug) .
To prevent a possible endless breakpoint matching loop, no break occurs for a breakpoint match on the first instruction
after returning from debug mode to background mode . Returning to background mode also enables all internal timer
functions .
17.2.5DebugModeSpecialConsiderations
The following are special considerations when using debug mode .
• Special caution should be exercised when using the Write Register command on register bits that globally affect
system operation (e .g ., IGE, STOP) . If the write register command is used to invoke stop mode (setting STOP = 1),
the RST pin may be asserted to reset the debug engine and return to the background mode of operation .
• Single stepping (‘Trace’) through any IGE bit change operation results in the debug engine overriding the bit change
since it retains the IGE bit setting captured when active debug mode was entered .
• Single stepping (‘Trace’) into an operation that sets STOP = 1 when IGE = 1 effectively allows enabled interrupts
normally capable of causing exit from stop mode to do so .
• Single stepping (‘Trace’) through any memory read instruction that reads from the utility ROM (such as ‘move Acc,’
@DP[0] with DP[0] set to 8000h) causes the memory read to return an incorrect value .
• Single stepping (‘Trace’) cannot be used when executing code from the utility ROM .
• Data memory allocation is important during system development if in-circuit debug is planned . The top 32-byte
memory location may be used by the debug service routine during debug mode . The data contents in these loca-
tions may be altered and cannot be recovered .
• One available stack location is needed for debug mode . If the stack is full when entering debug mode, the oldest
data in the stack is overwritten .
• Any signal sampling that relies upon the internal system clock (e .g ., counter inputs) can be unreliable since the
system clock is turned off inside active debug mode between debug mode commands .