Maxim Integrated MAX31782 - Manual (Page 78)

MaximIntegrated 8-10
MAX31782 User’s Guide
Revision 0; 8/11
8.2.2I 2 CMasterStatusRegister(I2CST�M)
Address: M1[01h]
*Set by hardware only.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name I2CBUS I2CBUSY — — I2CSPI I2CSCL I2CROI I2CGCI I2CNACKI — I2CAMI I2CTOI I2CSTRI I2CRXI I2CTXI I2CSRI
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access r* r* r r rw r* rw rw rw* r rw rw rw* rw* rw rw
BIT NAME DESCRIPTION
15 I2CBUS
I 2 C Master Bus Busy . This bit is set to 1 when a START/repeated START condition is detected and
cleared to 0 when the STOP condition is detected . This bit is reset to 0 when I2CEN = 0 . This bit is con-
trolled by hardware and is read only .
14 I2CBUSY
I 2 C Master Busy . This bit is used to indicate the current status of the I 2 C controller . The I2CBUSY is set
to 1 when the I 2 C controller is actively participating in a transaction . This bit is controlled by hardware
and is read only .
13:12 —– Reserved . The user should not write to these bits .
11 I2CSPI
I 2 C Master STOP Interrupt Flag . This bit is set to 1 when a STOP condition is detected . This bit must be
cleared to 0 by software once set . Setting this bit to 1 by software causes an interrupt if enabled .
10 I2CSCL
I 2 C Master SCL Status . This bit reflects the logic state of the SCL signal . This bit is set to 1 when SCL is
at a high logic level and cleared to 0 when SCL is at a low logic level . This bit is controlled by hardware
and is read only .
9 I2CROI
I 2 C Master Receiver Overrun Flag . This bit indicates a receive overrun when set to 1 . This bit is set to
1 if the receiver has received 2 bytes since the last software reading of I2CBUF_M . This bit can only
be cleared to 0 by software reading I2CBUF_M . Setting this bit to 1 by software causes an interrupt if
enabled .
8 I2CGCI This bit has no function when operating in master mode .
7 I2CNACKI
I 2 C Master NACK Interrupt Flag . This bit is set by hardware to a 1 if a NACK was received from a slave
or a 0 if an ACK was received from a slave . The setting of this bit to a 1 by hardware causes an interrupt
if enabled . This bit can be cleared to 0 by software once set .
This bit is set by hardware only .
6 —– Reserved . The user should not write to this bit .
5 I2CAMI This bit has no function when operating in master mode .
4 I2CTOI
I 2 C Master Timeout Interrupt Flag . This bit is set to a 1 if the I 2 C controller cannot generate a START or
STOP condition or the SCL low time is greater than the timeout value specified in the I2CTO_M register .
This bit must be cleared to 0 by software once set . Setting this bit to 1 by software causes an interrupt if
enabled .
3 I2CSTRI
I 2 C Master Clock Stretch Interrupt Flag . This bit indicates that the I 2 C master controller is operating with
clock stretching enabled and is currently holding the SCL clock signal low . The I 2 C controller releases
SCL after this bit has been cleared to 0 . This bit must be cleared to 0 by software once set . This bit is
set by hardware only .
2 I2CRXI
I 2 C Master Receive Ready Interrupt Flag . This bit indicates that a data byte has been received in
I2CBUF_M . This bit must be cleared by software once set . This bit is set by hardware only .
1 I2CTXI
I 2 C Master Transmit Complete Interrupt Flag . This bit indicates that an address or a data byte has been
successfully shifted out and the I 2 C controller has received an acknowledgment from the receiver (ACK
or NACK) . This bit must be cleared by software once set . Setting this bit to 1 by software causes an
interrupt if enabled .
0 I2CSRI
I 2 C Master START Interrupt Flag . This bit is set to 1 when a START condition (or restart) is detected .
This bit must be cleared to 0 by software once set . Setting this bit to 1 by software causes an interrupt if
enabled .