Maxim Integrated MAX31782 - Manual (Page 75)

MaximIntegrated 8-7
MAX31782 User’s Guide
Revision 0; 8/11
Following the 8th bit of data (least significant bit) being shifted to SDA, the SDA line will be released by the MAX31782
master controller . This allows the slave to signal an ACK or NACK during the 9th clock cycle . The MAX31782 I
2 C master
controller samples the acknowledge bit following the 9th SCL rising edge . After the acknowledge bit is sampled, the
MAX31782 I
2 C master controller will perform the following tasks:
• Set or clear the I2CNACKI flag to reflect the received acknowledge bit . The setting of I2CNACKI can generate an
interrupt if enabled .
• Set the I2CTXI flag to indicate that the I 2 C master controller transmit a complete byte . This can generate an interrupt
if enabled .
• Clear the I2CBUSY flag to indicate that the I 2 C master controller is not actively participating in the transfer of data .
8.1.9ReceivingData
The MAX31782 I 2 C master controller enters data reception mode after transmitting a slave address with the R/W bit
(I2CMODE) set to a 1 . The steps of data reception are shown in Figure 8-5 . After transmitting the slave address, the
master controller will switch to receiver mode and automatically begin outputting SCL clock pulses and shifting in data
from SDA .
When receiving data, the MAX31782 I
2 C master controller uses a double buffer consisting of the I2CBUF_M register
and the shift register . This allows the I 2 C module to continue receiving data while the previous data byte is being
processed . When a full byte of data (8 bits) has been received by the I 2 C master controller, the master must send an
acknowledgement to the slave . This occurs during the 9th clock cycle when the value in I2CACK is transmit to the slave .
After a complete byte (8 bits) of data are received, the I
2 C master controller will attempt to copy the received data from
the shift register to I2CBUF_M . There are two possible results from the I 2 C master controller’s attempt to copy the shift
register to I2CBUF_M .
1) If I2CBUF_M is empty, the I
2 C master controller will copy the data from the shift register into I2CBUF_M . The I2CRXI
flag will be set to indicate a received byte is ready to be read . The setting of I2CRXI can generate an interrupt if
enabled .
2) If I2CBUF_M is full, the data in the shift register cannot be copied into I2CBUF_M . This causes a receive overrun
condition . The receive overrun flag, I2CROI, will be set which can generate an interrupt if enabled . I2CBUF_M will
be full if it was not read by software following the reception of a previous byte .
After receiving a byte of data and the I2CRXI flag being set, it is up to software to read I2CBUF_M prior to a second
byte being received . Reading the I2CBUF_M register returns the received data and also clears I2CBUF_M . As long as
the previous byte of data is read from I2CBUF_M before the next byte has completed, receive overrun will not occur .
When receive overrun is detected and I2CROI bit is set, the MAX31782 master I
2 C controller will stop outputting SCL
clocks and not clock the acknowledge bit until the receive overrun condition is cleared . The receive overrun condition
and the I2CROI flag can only be cleared by software reading the first byte received from I2CBUF_M . When the receive
overrun condition is cleared, the I
2 C master controller will copy the second byte that was received into I2CBUF_M,
and again set I2CRXI to indicate a byte of data was received . The I 2 C master controller will resume clocking SCL after
satisfying SCL low time requirements .
The master I
2 C controller will continue to automatically clock bytes of data until any of the following conditions occur .
1) A receive overrun condition occurs .
2) A STOP command is issued (I2CSTOP = 1) prior to the master I
2 C controller beginning to clock a new byte .
3) The master I 2 C controller has clock stretching enabled and the clock is currently being held low by the master .
8.1.10I 2 CMasterClockStretching
The master I 2 C controller is capable of clock stretching at the end of each transfer cycle . Clock stretching is when SCL
is held low . If the I 2 C clock stretch enable bit (I2CSTREN) is set to a 1, the I 2 C controller holds SCL low after the clock
pulse defined by the I 2 C clock stretch select bit (I2CSTRS) . If I2CSTRS = 0, the I 2 C controller holds SCL low after the
falling edge of the 9th clock pulse . If I2CSTRS = 1, the I 2 C controller holds SCL low after the falling edge of the 8th
clock pulse . When the I 2 C controller is holding SCL low, the I 2 C clock stretch interrupt flag (I2CSTRI) is set, which can
generate an interrupt if enabled . The I 2 C slave controller holds SCL low until I2CSTRI is cleared to 0 by software .