2 module interrupt identification registers, 5 .2 module interrupt identification registers -5, 2moduleinterruptidentificationregisters – Maxim Integrated MAX31782 User Manual
Page 40
MaximIntegrated 5-5
MAX31782 User’s Guide
Revision 0; 8/11
5.2ModuleInterruptIdentificationRegisters
The MIIR registers are implemented to indicate which particular function within a peripheral module has caused the
interrupt . The MAX31782 has six peripheral modules, M0 to M5 . An MIIR register is implemented in each peripheral
module . The MIIR registers are 16-bit read-only registers and all of them default to 0000h on system reset .
Each defined bit in an MIIR register is the final interrupt from a specific function, i .e ., the interrupt enable bit(s) ANDed
with the interrupt flag(s) . A function can have multiple flags, but they all are ANDed with corresponding enable bits and
combined to create a single interrupt identification bit for that specific function . For example, the I
2
C master has several
interrupt sources; however, they all are combined to form a single identification bit, MIIR1 .I2CM . The individual register
bit functions are defined as follows .
5.2.1PeripheralModule0InterruptIdentificationRegister(MIIR0,M0[03h])
5.2.2PeripheralModule1InterruptIdentificationRegister(MIIR1,M1[04h])
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TB0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
BIT
NAME
DESCRIPTION
15:1
—
Reserved . A read returns 0 .
0
TB0
This bit is set when an interrupt is generated by the Timer/Counter B module .
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
I2CM_WU
I2CM
P6_7
P6_6
SVM
P6_4
P6_3
P6_2
P6_1
P6_0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
BIT
NAME
DESCRIPTION
15:10
—
Reserved . A read returns 0 .
9
I2CM_WU
This bit is set when there is a wake-up interrupt from the I
2
C master block . For this to occur, the I
2
C
master block must be operating as a slave . See
more details on this operation . The wake-up interrupt function is identical to the function described
for the I2CS_WU bit in MIIR2 .
8
I2CM
This bit is set when there is an interrupt from the I
2
C master block . The I
2
C interrupt is a combina-
tion of all interrupts defined in the I2CST_M register for the I
2
C master block . See
for more details on the individual interrupts .
7
P6_7
This bit is set when there is an external GPIO Interrupt at P6 .7 (slave I
2
C SDA) .
6
P6_6
This bit is set when there is an external GPIO Interrupt at P6 .6 (slave I
2
C SCL) .
5
SVM
This bit is set when there is an interrupt from supply voltage monitor (SVM) .
4
P6_4
This bit is set when there is an external interrupt at P6 .4 .
3
P6_3
This bit is set when there is an external interrupt at P6 .3 .
2
P6_2
This bit is set when there is an external interrupt at P6 .2 .
1
P6_1
This bit is set when there is an external interrupt at P6 .1 .
0
P6_0
This bit is set when there is an external interrupt at P6 .0 .