3 in-circuit debug peripheral registers, 17 .3 in-circuit debug peripheral registers -13, 3in-circuitdebugperipheralregisters – Maxim Integrated MAX31782 User Manual
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MaximIntegrated 17-13
MAX31782 User’s Guide
Revision 0; 8/11
17.3In-CircuitDebugPeripheralRegisters
The following peripheral registers are used to control the in-circuit debug mode of the MAX31782 . Addresses of regis-
ters are given as “Mx[yy],” where x is the module number (from 0 to 5 decimal) and yy is the register index (from 00h
to 1Fh hexadecimal) . Fields in the bit definition tables are defined as follows:
• Name: Symbolic names of bits or bit fields in this register .
• Reset: The value of each bit in this register following a standard reset . If this field reads “unchanged,” the given bit
is unaffected by standard reset . If this field reads “s,” the given bit does not have a fixed 0 or 1 reset value because
its value is determined by another internal state or external condition .
• POR: If present this field defines the value of each bit in this register following a power-on reset (as opposed to a
standard reset) . Some bits are unaffected by standard resets and are set/cleared by POR only .
• Access: Bits can be read-only (r) or read/write (rw) . Any special restrictions or conditions that could apply when
reading or writing this bit are detailed in the bit description .
17.3.1In-CircuitDebugTemp0Register(ICDT0,M2[18h])
This register is read/write accessible by the CPU only in background mode or debug mode . This register is intended
for use by the utility ROM routines as temporary storage to save registers that might otherwise have to be placed in the
stack .
17.3.2In-CircuitDebugTemp1Register(ICDT1,M2[19h])
This register is read/write accessible by the CPU only in background mode or debug mode . This register is intended
for use by the utility ROM routines as temporary storage to save registers that might otherwise have to be placed in the
stack .
s = special
s = special
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
ICDT0 .15 ICDT0 .14 ICDT0 .13 ICDT0 .12 ICDT0 .11 ICDT0 .10 ICDT0 .9
ICDT0 .8
ICDT0 .7
ICDT0 .6
ICDT0 .5
ICDT0 .4
ICDT0 .3
ICDT0 .2
ICDT0 .1
ICDT0 .0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
ICDT1 .15 ICDT1 .14 ICDT1 .13 ICDT1 .12 ICDT1 .11 ICDT1 .10 ICDT1 .9
ICDT1 .8
ICDT1 .7
ICDT1 .6
ICDT1 .5
ICDT1 .4
ICDT1 .3
ICDT1 .2
ICDT1 .1
ICDT1 .0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s