Rainbow Electronics ATmega163L User Manual
Features
Table of contents
Document Outline
- Features
- Pin Configurations
- Description
- Block Diagram
- Pin Descriptions
- Architectural Overview
- The General Purpose Register File
- The ALU - Arithmetic Logic Unit
- The In-System Self-programmable Flash Program Memory
- The SRAM Data Memory
- The Program and Data Addressing Modes
- Register Direct, Single Register Rd
- Register Direct, Two Registers Rd And Rr
- I/O Direct
- Data Direct
- Data Indirect With Displacement
- Data Indirect
- Data Indirect With Pre-decrement
- Data Indirect With Post-increment
- Constant Addressing Using The LPM and SPM Instructions
- Indirect Program Addressing, IJMP and ICALL
- Relative Program Addressing, RJMP and RCALL
- The EEPROM Data Memory
- Memory Access Times and Instruction Execution Timing
- I/O Memory
- Reset and Interrupt Handling
- Reset Sources
- Power-on Reset
- External Reset
- Brown-out Detection
- Watchdog Reset
- MCU Status Register - MCUSR
- Internal Voltage Reference
- Voltage Reference Enable Signals and Start-up Time
- Interrupt Handling
- Interrupt Response Time
- The General Interrupt Mask Register - GIMSK
- The General Interrupt Flag Register - GIFR
- The Timer/Counter Interrupt Mask Register - TIMSK
- The Timer/Counter Interrupt Flag Register - TIFR
- External Interrupts
- MCU Control Register - MCUCR
- Sleep Modes
- Calibrated Internal RC Oscillator
- Timer / Counters
- Timer/Counter Prescalers
- 8-bit Timer/Counter0
- 16-bit Timer/Counter1
- Timer/Counter1 Control Register A - TCCR1A
- Timer/Counter1 Control Register B - TCCR1B
- Timer/Counter1 - TCNT1H and TCNT1L
- TCNT1 Timer/Counter1 Write:
- TCNT1 Timer/Counter1 Read:
- Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL
- Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL
- Timer/Counter1 Input Capture Register - ICR1H and ICR1L
- Timer/Counter1 in PWM Mode
- 8-Bit Timer/Counter 2
- Watchdog Timer
- EEPROM Read/Write Access
- Serial Peripheral Interface - SPI
- UART
- 2-wire Serial Interface (Byte Oriented)
- The 2-wire Serial Interface Bit Rate Register - TWBR
- The 2-wire Serial Interface Control Register - TWCR
- The 2-wire Serial Interface Status Register - TWSR
- The 2-wire Serial Interface Data Register - TWDR
- The 2-wire Serial Interface (Slave) Address Register - TWAR
- 2-wire Serial Interface Modes
- Master Transmitter Mode
- Master Receiver Mode
- Slave Receiver Mode
- Slave Transmitter Mode
- Miscellaneous States
- The Analog Comparator
- Analog to Digital Converter
- I/O-Ports
- Memory Programming
- Boot Loader Support
- Self-programming the Flash
- Performing Page Erase by SPM
- Fill the Temporary Buffer (Page Load)
- Perform a Page Write
- Consideration while Updating BLS
- Wait for SPM Instruction to Complete
- Instruction Word Read after Page Erase, Page Write, and Lock-bit Write
- Avoid Reading the Application Section During Self-programming
- Boot Loader Lock-bits
- Setting the Boot Loader Lock Bits by SPM
- Reading the Fuse and Lock Bits from Software
- EEPROM Write Prevents Writing to SPMCR
- Addressing the Flash During Self-programming
- Store Program Memory Control Register - SPMCR
- Preventing Flash Corruption
- Program And Data Memory Lock Bits
- Fuse Bits
- Signature Bytes
- Calibration Byte
- Parallel Programming
- Parallel Programming Characteristics
- Serial Downloading
- Serial Programming Characteristics
- Electrical Characteristics
- DC Characteristics
- External Clock Drive Waveforms
- External Clock Drive
- 2-wire Serial Interface Characteristics
- Typical Characteristics - Preliminary Data
- Register Summary
- Instruction Set Summary
- Ordering Information