Rainbow Electronics ATmega163L - Manual (Page 49)

ATmega163(L)
49
• Bit 2 - TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set (one). When TCNT2 has been
updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that
TCNT2 is ready to be updated with a new value.
•
Bit 1 - OCR2UB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set (one). When OCR2 has been
updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that
OCR2 is ready to be updated with a new value.
•
Bit 0 - TCR2UB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set (one). When TCCR2 has been
updated from the temporary storage register, this bit is cleared (zero) by hardware. A logical zero in this bit indicates that
TCCR2 is ready to be updated with a new value.
If a write is performed to any of the three Timer/Counter2 registers while its update busy flag is set (one), the updated value
might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is
read. When reading OCR2 or TCCR2, the value in the temporary storage register is read.
Asynchronous Operation of Timer/Counter2
When Timer/Counter2 operates asynchronously, some considerations must be taken.
• Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers
TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is:
1. Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2.
2. Select clock source by setting AS2 as appropriate.
3. Write new values to TCNT2, OCR2, and TCCR2.
4. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB.
5. Enable interrupts, if needed.
• The oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may
result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be more than four times the oscillator
frequency.
• When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register, and
latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary
register have been transferred to its destination. Each of the three mentioned registers have their individual temporary
register, which means that e.g. writing to TCNT2 does not disturb an OCR2 write in progress. To detect that a transfer to
the destination register has taken place, the Asynchronous Status Register - ASSR has been implemented.
• When entering Power Save mode after having written to TCNT2, OCR2, or TCCR2, the user must wait until the written
register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode
before the changes are effective. This is particularly important if the Output Compare2 interrupt is used to wake up the
device, since the output compare function is disabled during writing to OCR2 or TCNT2. If the write cycle is not finished,
and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a compare match
interrupt, and the MCU will not wake up.
• If Timer/Counter2 is used to wake the device up from Power Save mode, precautions must be taken if the user wants to
re-enter Power Save mode: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-
entering Power Save mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up.
If the user is in doubt whether the time before re-entering Power Save is sufficient, the following algorithm can be used to
ensure that one TOSC1 cycle has elapsed:
1. Write a value to TCCR2, TCNT2, or OCR2.
2. Wait until the corresponding Update Busy flag in ASSR returns to zero.
3. Enter Power Save mode.