Rainbow Electronics ATmega163L - Manual (Page 70)

ATmega163(L)
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Note: Both the receiver and the transmitter can stretch the low period of the SCL line when waiting for user response, thereby reduc-
ing the average bit rate.
TWBR should be set to a value higher than 7 to ensure correct 2-wire Serial Bus functionality. The bus alignment adjustion
is automatically inserted by the 2-wire Serial Interface, and ensures the validity of setup and hold times on the bus for any
TWBR value higher than 7. This adjustment may vary from 200 ns to 600 ns depending on bus loads and drive capabilities
of the devices connected to the bus.
The 2-wire Serial Interface Control Register - TWCR
• Bit 7 - TWINT: 2-wire Serial Interface Interrupt Flag
This bit is set by hardware when the 2-wire Serial Interface has finished its current job and expects application software
response. If the I-bit in the SREG and TWIE in the TWCR register are set (one), the MCU will jump to the interrupt vector at
address $011. While the TWINT flag is set, the bus SCL clock line low period is stretched. The TWINT flag must be cleared
by software by writing a logic one to it. Note that this flag is not automaticaly cleared by hardware when executing the inter-
rupt routine. Also note that clearing this flag starts the operation of the 2-wire Serial Interface, so all accesses to the 2-wire
Serial Interface Address Register - TWAR, 2-wire Serial Interface Status Register - TWSR, and 2-wire Serial Interface Data
Register - TWDR must be complete before clearing this flag.
•
Bit 6 - TWEA: 2-wire Serial Interface Enable Acknowledge Flag
TWEA flag controls the generation of the acknowledge pulse. If the TWEA bit is set, the ACK pulse is generated on the 2-
wire Serial Bus if the following conditions are met:
1. The device’s own slave address has been received.
2. A general call has been received, while the TWGCE bit in the TWAR is set.
3. A data byte has been received in master receiver or slave receiver mode.
By setting the TWEA bit low, the device can be virtually disconnected from the 2-wire Serial Bus temporarily. Address rec-
ognition can then be resumed by setting the TWEA bit again.
•
Bit 5 - TWSTA: 2-wire Serial Bus START Condition Flag
The TWSTA flag is set by the application when it desires to become a master on the 2-wire Serial Bus. The 2-wire Serial
Interface hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the
bus is not free, the 2-wire Serial Interface waits until a STOP condition is detected, and then generates a new START con-
dition to claim the bus Master status.
•
Bit 4 - TWSTO: 2-wire Serial Bus STOP Condition Flag
TWSTO is a stop condition flag. In Master mode setting the TWSTO bit in the control register will generate a STOP condi-
tion on the 2-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In
slave mode setting the TWSTO bit can be used to recover from an error condition. No stop condition is generated on the
bus then, but the 2-wire Serial Interface returns to a well-defined unaddressed slave mode and releases the SCL and SDA
lines to a high impedance state.
•
Bit 3 - TWWC: 2-wire Serial Bus Write Collision Flag
The TWWC bit is set when attempting to write to the 2-wire Serial Interface Data Register - TWDR when TWINT is low.
This flag is cleared by writing the TWDR register when TWINT is high.
•
Bit 2 - TWEN: 2-wire Serial Interface Enable Bit
The TWEN bit enables 2-wire Serial Interface operation. If this bit is cleared (zero), the bus outputs SDA and SCL are set to
high impedance state, and the input signals are ignored. The interface is activated by setting this bit (one).
•
Bit 1 - Res: Reserved Bit
This bit is a reserved bit in the ATmega163 and will always read as zero.
•
Bit 0 - TWIE: 2-wire Serial Interface Interrupt Enable
When this bit is enabled, and the I-bit in SREG is set, the 2-wire Serial Interface interrupt will be activated for as long as the
TWINT flag is high.
Bit 7 6 5 4 3 2 1 0
$36 ($56) TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE TWCR
Read/Write R/W R/W R/W R/W R R/W R R/W
Initial value 0 0 0 0 0 0 0 0