beautypg.com

Architectural overview, Atmega163(l), Avr atmega163 architecture – Rainbow Electronics ATmega163L User Manual

Page 7

background image

ATmega163(L)

7

Architectural Overview

The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access
time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock
cycle.

Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling
efficient address calculations. One of the three address pointers is also used as the address pointer for look-up tables in
Flash program memory. These added function registers are the 16-bits X-register, Y-register, and Z-register.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 5 shows the ATmega163 AVR Enhanced RISC microcontroller
architecture.

In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the register file is assigned the 32 lowest Data Space addresses ($00 - $1F), allowing them
to be accessed as though they were ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-
converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following
those of the register file, $20 - $5F.

Figure 5. The ATmega163 AVR RISC Architecture

8K X 16

Program

Memory

Instruction

Register

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

Interrupt

Unit

SPI

Unit

8-bit

Timer/Counter

Watchdog

Timer

A/D Converter

Analog

Comparator

32

I/O Lines

512 x 8
EEPROM

Data Bus 8-bit

AVR ATmega163 Architecture

2-Wire Serial

Interface

16-bit

Timer/Counter

with PWM

8-bit

Timer/Counter

with PWM

1024 x 8

Data

SRAM

Direct Addressing

Indirect Addressing

Serial

UART