Rainbow Electronics ATmega163L - Manual (Page 58)

ATmega163(L)
58
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits
CPHA and CPOL. The SPI data transfer formats are shown in Figure 43 and Figure 44.
Figure 43. SPI Transfer Format with CPHA = 0 and DORD = 0
Figure 44. SPI Transfer Format with CPHA = 1 and DORD = 0
SPI Control Register - SPCR
• Bit 7 - SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the if the global interrupt enable
bit in SREG is set.
•
Bit 6 - SPE: SPI Enable
When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations.
•
Bit 5 - DORD: Data Order
When the DORD bit is set (one), the LSB of the data word is transmitted first.
When the DORD bit is cleared (zero), the MSB of the data word is transmitted first.
•
Bit 4 - MSTR: Master/Slave Select
This bit selects Master SPI mode when set (one), and Slave SPI mode when cleared (zero). If SS is configured as an input
and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to
set MSTR to re-enable SPI master mode.
•
Bit 3 - CPOL: Clock Polarity
When this bit is set (one), SCK is high when idle. When CPOL is cleared (zero), SCK is low when idle. Refer to Figure 43
and Figure 44 for additional information.
Bit 7 6 5 4 3 2 1 0
$0D ($2D) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0