Rainbow Electronics ATmega163L - Manual (Page 28)

ATmega163(L)
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• Bit 6 - INTF0: External Interrupt Flag0
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit
in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt
routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when
INT0 is configured as a level interrupt.
•
Bits 5..0 - Res: Reserved Bits
These bits are reserved bits in the ATmega163 and always read as zero.
The Timer/Counter Interrupt Mask Register - TIMSK
• Bit 7 - OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match inter-
rupt is enabled. The corresponding interrupt (at vector $006) is executed if a compare match in Timer/Counter2 occurs, i.e.
when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
•
Bit 6 - TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is
enabled. The corresponding interrupt (at vector $008) is executed if an overflow in Timer/Counter2 occurs, i.e. when the
TOV2 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
•
Bit 5 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event
Interrupt is enabled. The corresponding interrupt (at vector $00A) is executed if a capture triggering event occurs on PD6
(ICP), i.e. when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
•
Bit 4 - OCIE1A: Timer/Counter1 Output CompareA Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match
interrupt is enabled. The corresponding interrupt (at vector $00C) is executed if a CompareA match in Timer/Counter1
occurs, i.e. when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
•
Bit 3 - OCIE1B: Timer/Counter1 Output CompareB Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match
interrupt is enabled. The corresponding interrupt (at vector $00E) is executed if a CompareB match in Timer/Counter1
occurs, i.e. when the OCF1B bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
•
Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is
enabled. The corresponding interrupt (at vector $010) is executed if an overflow in Timer/Counter1 occurs, i.e. when the
TOV1 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
•
Bit 1 - Res: Reserved Bit
This bit is a reserved bit in the ATmega163 and always reads as zero.
•
Bit 0 - TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is
enabled. The corresponding interrupt (at vector $012) is executed if an overflow in Timer/Counter0 occurs, i.e. when the
TOV0 bit is set in the Timer/Counter Interrupt Flag Register - TIFR.
Bit 7 6 5 4 3 2 1 0
$39 ($59) OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 - TOIE0 TIMSK
Read/Write R/W R/W R/W R/W R/W R/W R R/W
Initial value 0 0 0 0 0 0 0 0