Rainbow Electronics ATmega163L - Manual (Page 53)

ATmega163(L)
53
EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space.
The write access time is in the range of 1.9 - 3.8 ms, depending on the V
CC
voltages. See Table 24 for details. A self-timing
function, however, lets the user software detect when the next byte can be written. If the user code contains code that
writes the EEPROM, some precautions must be taken. In heavily filtered power supplies, V
CC
is likely to rise or fall slowly
on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for
the clock frequency used. CPU operation under these conditions is likely to cause the program counter to perform uninten-
tional jumps and potentially execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an
external under-voltage reset circuit or the internal BOD in this case.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of
the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the
EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
The EEPROM Address Register - EEARH and EEARL
• Bits 15..9 - Res: Reserved Bits
These bits are reserved bits in the ATmega163 and will always read as zero.
•
Bits 8..0 - EEAR8..0: EEPROM Address
The EEPROM Address Registers - EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space.
The EEPROM data bytes are addressed linearly between 0 and 511. The initial value of EEAR is undefined. A proper value
must be written before the EEPROM may be accessed.
The EEPROM Data Register - EEDR
• Bits 7..0 - EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given
by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the
address given by EEAR.
The EEPROM Control Register - EECR
• Bits 7..4 - Res: Reserved Bits
These bits are reserved bits in the ATmega163 and will always read as zero.
Bit 15 14 13 12 11 10 9 8
$1F ($3F) - - - - - - - EEAR8 EEARH
$1E ($3E) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
7 6 5 4 3 2 1 0
Read/Write R R R R R R R R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 X
X X X X X X X X
Bit 7 6 5 4 3 2 1 0
$1D ($3D) MSB LSB EEDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
$1C ($3C) - - - - EERIE EEMWE EEWE EERE EECR
Read/Write R R R R R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0