Rainbow Electronics ATmega163L - Manual (Page 30)

ATmega163(L)
30
MCU Control Register - MCUCR
The MCU Control Register contains control bits for general MCU functions.
• Bit 7 - Res: Reserved Bit
This bit is a reserved bit in the ATmega163 and always reads as zero.
•
Bit 6 - SE: Sleep Enable
The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the
MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just
before the execution of the SLEEP instruction.
•
Bits 5,4 - SM1/SM0: Sleep Mode Select bits 1 and 0
These bits select between the three available sleep modes as shown in Table 7.
• Bits 3, 2 - ISC11, ISC10: Interrupt Sense Control 1 bit 1 and bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the
GIMSK are set. The level and edges on the external INT1 pin that activate the interrupt are defined in Table 8. The value on
the INT1 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.
• Bit 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are
set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9. The value on the INT0
pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period
will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the
low level must be held until the completion of the currently executing instruction to generate an interrupt.
Bit 7 6 5 4 3 2 1 0
$35 ($55) - SE SM1 SM0 ISC11 ISC10 ISC01 ISC00 MCUCR
Read/Write R R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Table 7. Sleep Mode Select
SM1 SM0 Sleep Mode
0 0 Idle
0 1 ADC Noise Reduction
1 0 Power-down
1 1 Power Save
Table 8. Interrupt 1 Sense Control
ISC11 ISC10 Description
0 0 The low level of INT1 generates an interrupt request.
0 1 Any logical change on INT1 generates an interrupt request.
1 0 The falling edge of INT1 generates an interrupt request.
1 1 The rising edge of INT1 generates an interrupt request.