Atmega163(l) – Rainbow Electronics ATmega163L User Manual
Page 40
ATmega163(L)
40
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1
is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset
with the written value.
Timer/Counter1 Output Compare Register - OCR1AH and OCR1AL
Timer/Counter1 Output Compare Register - OCR1BH and OCR1BL
The output compare registers are 16-bit read/write registers.
The Timer/Counter1 Output Compare Registers contain the data to be continuously compared with Timer/Counter1.
Actions on compare matches are specified in the Timer/Counter1 Control and Status register. A compare match occurs
only if Timer/Counter1 counts to the OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same
value does not generate a compare match.
A compare match will set the compare interrupt flag in the CPU clock cycle following the compare event.
Since the Output Compare Registers - OCR1A and OCR1B - are 16-bit registers, a temporary register TEMP is used when
OCR1A/B are written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH
or OCR1BH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL,
the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high byte OCR1AH or OCR1BH
must be written first for a full 16-bit register write operation.
The TEMP register is also used when accessing TCNT1 and ICR1. If the main program and also interrupt routines perform
access to registers using TEMP, interrupts must be disabled during access from the main program and interrupt routines.
Timer/Counter1 Input Capture Register - ICR1H and ICR1L
The input capture register is a 16-bit read-only register.
When the rising or falling edge (according to the input capture edge setting - ICES1) of the signal at the input capture pin -
ICP - is detected, the current value of the Timer/Counter1 Register - TCNT1 - is transferred to the Input Capture Register -
ICR1. At the same time, the input capture flag - ICF1 - is set (one).
Bit
15
14
13
12
11
10
9
8
$2B ($4B)
MSB
OCR1AH
$2A ($4A)
LSB
OCR1AL
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
$29 ($49)
MSB
OCR1BH
$28 ($48)
LSB
OCR1BL
7
6
5
4
3
2
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
$27 ($47)
MSB
ICR1H
$26 ($46)
LSB
ICR1L
7
6
5
4
3
2
1
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0