The spi status register - spsr, The spi data register - spdr, Atmega163(l) – Rainbow Electronics ATmega163L User Manual
Page 59
ATmega163(L)
59
•
Bit 2 - CPHA: Clock Phase
Refer to Figure 43 and Figure 44 for the functionality of this bit.
•
Bits 1,0 - SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect on the slave. The
relationship between SCK and the Oscillator Clock frequency f
ck
is shown in the following table:
The SPI Status Register - SPSR
•
Bit 7 - SPIF : SPI Interrupt Flag
When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR is set (one) and
global interrupts are enabled. If SS is an input and is driven low when the SPI is in master mode, this will also set the SPIF
flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is
cleared by first reading the SPI status register with SPIF set (one), then accessing the SPI Data Register (SPDR).
•
Bit 6 - WCOL : Write COLlision Flag
The WCOL bit is set if the SPI data register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are
cleared (zero) by first reading the SPI Status Register with WCOL set (one), and then accessing the SPI Data Register.
•
Bit 5..1 - Res: Reserved Bits
These bits are reserved bits in the ATmega163 and will always read as zero.
•
Bit 0 - SPI2X: Double SPI Speed Bit
When this bit is set (one) the SPI speed (SCK Frequency) will be doubled when the SPI is in master mode (see Table 26).
This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only
guaranteed to work at f
ck
/ 4 or lower.
The SPI interface on the ATmega163 is also used for program memory and EEPROM downloading or uploading. See page
133 for serial programming and verification.
The SPI Data Register - SPDR
The SPI Data Register is a read/write register used for data transfer between the register file and the SPI Shift register.
Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
Table 26. Relationship Between SCK and the Oscillator Frequency
SPI2X
SPR1
SPR0
SCK Frequency
0
0
0
f
ck
/
4
0
0
1
f
ck
/
16
0
1
0
f
ck
/
64
0
1
1
f
ck
/
128
1
0
0
f
ck
/
2
1
0
1
f
ck
/
8
1
1
0
f
ck
/
32
1
1
1
f
ck
/
64
Bit
7
6
5
4
3
2
1
0
$0E ($2E)
SPIF
WCOL
-
-
-
-
-
SPI2X
SPSR
Read/Write
R
R
R
R
R
R
R
R/W
Initial value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
$0F ($2F)
MSB
LSB
SPDR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
X
X
X
X
X
X
X
X
Undefined