Rainbow Electronics ATmega163L - Manual (Page 54)

ATmega163(L)
54
• Bit 3 - EERIE: EEPROM Ready Interrupt Enable
When the I bit in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled. When cleared (zero), the inter-
rupt is disabled. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared (zero).
•
Bit 2 - EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set(one)
setting EEWE will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect.
When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description
of the EEWE bit for an EEPROM write procedure.
•
Bit 1 - EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up,
the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical one is written
to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the
EEPROM (the order of steps 2 and 3 is not essential):
1. Wait until EEWE becomes zero.
2. Write new EEPROM address to EEAR (optional).
3. Write new EEPROM data to EEDR (optional).
4. Write a logical one to the EEMWE bit in EECR.
5. Within four clock cycles after setting EEMWE, write a logical one to EEWE.
Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will
time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR regis-
ter will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag
cleared during the 4 last steps to avoid these problems.
When the write access time (see Table 24) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software
can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for four cycles
before the next instruction is executed.
•
Bit 0 - EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the
EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the
EEDR register. The EEPROM read access takes one instruction, and there is no need to poll the EERE bit. When EERE
has been set, the CPU is halted for two cycles before the next instruction is executed.
The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is not possible to
set the EERE bit, nor to change the EEAR register.
The calibrated oscillator is used to time the EEPROM accesses. Table 24 lists the typical programming time for EEPROM
access from the CPU
Preventing EEPROM Corruption
During periods of low V
CC,
the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the
EEPROM to operate properly. These issues are the same as for board level systems using the EEPROM, and the same
design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence
to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incor-
rectly, if the supply voltage for executing instructions is too low.
EEPROM data corruption can easily be avoided by following these design recommendations (one is sufficient):
Table 24. EEPROM Programming Time.
Symbol
Number of Calibrated RC-
oscillator Cycles Min. Programming Time Max. Programming Time
EEPROM write (from CPU) 2048 1.9 ms 3.8 ms